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2025-11-24RISC-V: KVM: Introduce KVM_EXIT_FAIL_ENTRY_NO_VSFILEBillXiang2-1/+3
Currently, we return CSR_HSTATUS as hardware_entry_failure_reason when kvm_riscv_aia_alloc_hgei failed in KVM_DEV_RISCV_AIA_MODE_HWACCEL mode, which is vague so it is better to return a well defined value KVM_EXIT_FAIL_ENTRY_NO_VSFILE provided via uapi/asm/kvm.h. Signed-off-by: BillXiang <xiangwencheng@lanxincomputing.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250923053851.32863-1-xiangwencheng@lanxincomputing.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-24RISC-V: KVM: Add SBI MPXY extension support for GuestAnup Patel4-0/+13
The SBI MPXY extension is a platform-level functionality so KVM only needs to forward SBI MPXY calls to KVM user-space. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20251017155925.361560-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-24RISC-V: KVM: Add separate source for forwarded SBI extensionsAnup Patel4-19/+28
Add a separate source vcpu_sbi_forward.c for SBI extensions which are entirely forwarded to KVM user-space. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20251017155925.361560-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-24RISC-V: KVM: Convert kvm_riscv_vcpu_sbi_forward() into extension handlerAnup Patel6-50/+14
All uses of kvm_riscv_vcpu_sbi_forward() also updates retdata->uexit so to further reduce code duplication move retdata->uexit assignment to kvm_riscv_vcpu_sbi_forward() and convert it into SBI extension handler. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20251017155925.361560-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-23riscv: dts: sifive: unmatched: Add PWM controlled fansRené Rebe1-0/+10
This adds the two PWM-controlled fans of the HiFive Unmatched board to the device tree. Signed-off-by: René Rebe <rene@exactco.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-23Merge tag 'perf-urgent-2025-11-23' of ↵Linus Torvalds1-2/+0
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf fixes from Ingo Molnar: "Fix perf CPU-clock counters, and address a static checker warning" * tag 'perf-urgent-2025-11-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf: Fix 0 count issue of cpu-clock perf/x86/intel/uncore: Remove superfluous check
2025-11-22Merge tag 'mips-fixes_6.18_1' of ↵Linus Torvalds4-46/+78
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Thomas Bogendoerfer: - Fix CPU type in DT for econet - Fix for Malta PCI MMIO breakage for SOC-it - Fix TLB shutdown caused by iniital uniquification - Fix random seg faults due to missed vdso storage requirement * tag 'mips-fixes_6.18_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: kernel: Fix random segmentation faults MIPS: mm: Prevent a TLB shutdown on initial uniquification mips: dts: econet: fix EN751221 core type MIPS: Malta: Fix !EVA SOC-it PCI MMIO
2025-11-22x86/{boot,mtrr}: Remove unused function declarationsYue Haibing2-6/+0
Commits 28be1b454c2b ("x86/boot: Remove unused copy_*_gs() functions") 34d2819f2078 ("x86, mtrr: Remove unused mtrr/state.c") removed the functions but left the prototypes. Remove them. [ bp: Merge into a single patch. ] Signed-off-by: Yue Haibing <yuehaibing@huawei.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20251120121037.1479334-1-yuehaibing@huawei.com
2025-11-22Merge tag 'riscv-for-linus-6.18-rc7' of ↵Linus Torvalds2-2/+6
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Paul Walmsley: - Correct the MIPS RISC-V/JEDEC vendor ID - Fix the system shutdown behavior in the legacy case where CONFIG_RISCV_SBI_V01 is set, but the firmware implementation doesn't support the older v0.1 system shutdown method - Align some tools/ macro definitions with the corresponding kernel headers * tag 'riscv-for-linus-6.18-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: tools: riscv: Fixed misalignment of CSR related definitions riscv: sbi: Prefer SRST shutdown over legacy riscv: Update MIPS vendor id to 0x127
2025-11-22crypto: ansi_cprng - Remove unused ansi_cprng algorithmEric Biggers84-84/+0
Remove ansi_cprng, since it's obsolete and unused, as confirmed at https://lore.kernel.org/r/aQxpnckYMgAAOLpZ@gondor.apana.org.au/ This was originally added in 2008, apparently as a FIPS approved random number generator. Whether this has ever belonged upstream is questionable. Either way, ansi_cprng is no longer usable for this purpose, since it's been superseded by the more modern algorithms in crypto/drbg.c, and FIPS itself no longer allows it. (NIST SP 800-131A Rev 1 (2015) says that RNGs based on ANSI X9.31 will be disallowed after 2015. NIST SP 800-131A Rev 2 (2019) confirms they are now disallowed.) Therefore, there is no reason to keep it around. Suggested-by: Herbert Xu <herbert@gondor.apana.org.au> Cc: Haotian Zhang <vulab@iscas.ac.cn> Cc: Neil Horman <nhorman@tuxdriver.com> Signed-off-by: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-11-22riscv: dts: allwinner: d1: fix vlenb propertySergey Matyukevich1-1/+1
According to [1], the C906 vector registers are 128 bits wide. The 'thead,vlenb' property specifies the vector register length in bytes, so its value must be set to 16. [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Fixes: ce1daeeba600 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree") Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-22bpf: arm64: Add support for indirect jumpsPuranjay Mohan1-0/+4
Add support for a new instruction BPF_JMP|BPF_X|BPF_JA, SRC=0, DST=Rx, off=0, imm=0 which does an indirect jump to a location stored in Rx. The register Rx should have type PTR_TO_INSN. This new type assures that the Rx register contains a value (or a range of values) loaded from a correct jump table – map of type instruction array. ARM64 JIT supports indirect jumps to all registers through the A64_BR() macro, use it to implement this new instruction. Signed-off-by: Puranjay Mohan <puranjay@kernel.org> Reviewed-by: Anton Protopopov <a.s.protopopov@gmail.com> Acked-by: Xu Kuohai <xukuohai@huawei.com> Link: https://lore.kernel.org/r/20251117130732.11107-3-puranjay@kernel.org Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2025-11-22bpf: arm64: Add support for instructions arrayPuranjay Mohan1-0/+7
Add support for the instructions array map type in the arm64 JIT by calling bpf_prog_update_insn_ptrs() with the offsets that map xlated_offset to the jited_offset in the final image. arm64 JIT already has this offset array which was being used for bpf_prog_fill_jited_linfo() and can be used directly for bpf_prog_update_insn_ptrs. Signed-off-by: Puranjay Mohan <puranjay@kernel.org> Reviewed-by: Anton Protopopov <a.s.protopopov@gmail.com> Acked-by: Xu Kuohai <xukuohai@huawei.com> Link: https://lore.kernel.org/r/20251117130732.11107-2-puranjay@kernel.org Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2025-11-22arm64: dts: rockchip: enable RTC for 100ASK DshanPi A1Chukun Pan1-0/+9
Enable RTC support for the 100ASK DshanPi A1 board. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://patch.msgid.link/20251120120011.279104-6-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-22arm64: dts: rockchip: enable USB for 100ASK DshanPi A1Chukun Pan1-0/+13
Enable USB support for the 100ASK DshanPi A1 board. Note that the HUSB311 Type-C chip is not supported. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://patch.msgid.link/20251120120011.279104-5-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-22arm64: dts: rockchip: enable button for 100ASK DshanPi A1Chukun Pan1-0/+67
The 100ASK DshanPi A1 board has three ADC buttons and one GPIO button. Enable them. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://patch.msgid.link/20251120120011.279104-4-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-22arm64: dts: rockchip: add mmc aliases for 100ASK DshanPi A1Chukun Pan1-0/+2
Add missing MMC aliases for 100ASK DshanPi A1 board. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://patch.msgid.link/20251120120011.279104-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-22arm64: dts: rockchip: remove mmc max-frequency for 100ASK DshanPi A1Chukun Pan1-2/+0
The max-frequency property is already defined in the mmc node of rk3576.dtsi. Remove the redundant definition. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://patch.msgid.link/20251120120011.279104-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-22arm64: dts: rockchip: Enable i2c2 on Orange Pi 3BMichael Opdenacker1-0/+5
Enable the "i2c2" bus on header pins 3 (I2C_SDA_M1) and 5 (I2C2_SCL_M1) of the Orange Pi 3B board. As documented on http://www.orangepi.org/img/pi3b/0719-pi3b-19.png, such pins are the only ones offering I2C functionality without conflicting with other SoC blocks. Signed-off-by: Michael Opdenacker <michael.opdenacker@rootcommit.com> Link: https://patch.msgid.link/20251120-orangepi3-enable-i2c2-v1-1-2e023a74012a@rootcommit.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-22x86,fs/resctrl: Implement "io_alloc" enable/disable handlersBabu Moger2-0/+45
"io_alloc" is the generic name of the new resctrl feature that enables system software to configure the portion of cache allocated for I/O traffic. On AMD systems, "io_alloc" resctrl feature is backed by AMD's L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Introduce the architecture-specific functions that resctrl fs should call to enable, disable, or check status of the "io_alloc" feature. Change SDCIAE state by setting (to enable) or clearing (to disable) bit 1 of MSR_IA32_L3_QOS_EXT_CFG on all logical processors within the cache domain. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://patch.msgid.link/9e9070100c320eab5368e088a3642443dee95ed7.1762995456.git.babu.moger@amd.com
2025-11-22Merge tag 'omap-for-v6.19/soc-signed' of ↵Arnd Bergmann2-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/arm ARM: OMAP2+: Fix falg->flag typo in omap_smc2() * tag 'omap-for-v6.19/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap: ARM: OMAP2+: Fix falg->flag typo in omap_smc2() Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-22ARM: gemini: fix typos in commentsJulia Lawall1-1/+1
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20251023204737.2716443-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-22x86,fs/resctrl: Detect io_alloc featureBabu Moger1-0/+7
AMD's SDCIAE (SDCI Allocation Enforcement) PQE feature enables system software to control the portions of L3 cache used for direct insertion of data from I/O devices into the L3 cache. Introduce a generic resctrl cache resource property "io_alloc_capable" as the first part of the new "io_alloc" resctrl feature that will support AMD's SDCIAE. Any architecture can set a cache resource as "io_alloc_capable" if a portion of the cache can be allocated for I/O traffic. Set the "io_alloc_capable" property for the L3 cache resource on x86 (AMD) systems that support SDCIAE. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://patch.msgid.link/df85a9a6081674fd3ef6b4170920485512ce2ded.1762995456.git.babu.moger@amd.com
2025-11-22x86/resctrl: Add SDCIAE feature in the command line optionsBabu Moger1-0/+2
Add a kernel command-line parameter to enable or disable the exposure of the L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) hardware feature to resctrl. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://patch.msgid.link/c623edf7cb369ba9da966de47d9f1b666778a40e.1762995456.git.babu.moger@amd.com
2025-11-22x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation ↵Babu Moger3-0/+4
Enforcement Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to control the portion of the L3 cache used for SDCI. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register, where n is the maximum supported CLOSID. Add CPUID feature bit that can be used to configure SDCIAE. The SDCIAE feature details are documented in: AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). available at https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/83ca10d981c48e86df2c3ad9658bb3ba3544c763.1762995456.git.babu.moger@amd.com
2025-11-21Merge tag 'v6.19-rockchip-defconfig64-1' of ↵Arnd Bergmann1-0/+3
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/defconfig Rockchip support for basic camera interface (CIF) and Synopsis DW-DP driver, as well as the CEC extension to the DW-HDMI-QP driver. * tag 'v6.19-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: defconfig: enable rockchip camera interface arm64: defconfig: Enable DW HDMI QP CEC support arm64: defconfig: Enable Rockchip extensions for Synopsys DW DP Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'qcom-arm64-defconfig-for-6.19' of ↵Arnd Bergmann1-0/+33
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig Qualcomm Arm64 defconfig updates for v6.19 Enable config options for the hardare used across Fairphone 3, 4, and 5. Then enable Novatek display panels founds on Xiaomi Pocophone F1, and the SM8750 MTP, eUSB2 PHY found in SM8750, NSS clock controller found in IPQ5424, the SX150x gpio expander used in QCS615 reference device, and the support for UFS inline crypto. * tag 'qcom-arm64-defconfig-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: defconfig: Enable SX150x GPIO expander driver arm64: defconfig: Build NSS clock controller driver for IPQ5424 arm64: defconfig: Enable SCSI UFS Crypto and Block Inline encryption drivers arm64: defconfig: Add M31 eUSB2 PHY config arm64: defconfig: Enable configs for Fairphone 3, 4, 5 smartphones arm64: defconfig: Enable two Novatek display panels for MTP8750 and Tianma Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'omap-for-v6.19/defconfig-signed' of ↵Arnd Bergmann1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/defconfig multi_v7_defconfig: Enable TI PRU Ethernet driver * tag 'omap-for-v6.19/defconfig-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap: ARM: multi_v7_defconfig: Enable TI PRU Ethernet driver Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'at91-defconfig-6.19' of ↵Arnd Bergmann1-1/+1
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/defconfig Microchip AT91 defconfig updates for v6.19 This update includes: - CONFIG_MMC_SPI is set to module for at91_dt_defconfig * tag 'at91-defconfig-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: at91_dt_defconfig: set MMC_SPI to module Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'imx-defconfig-6.19' of ↵Arnd Bergmann2-0/+7
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/defconfig i.MX defconfig changes for 6.19: - Enable sound drivers for imx28-amarula-rmm in mxs_defconfig - Enable i.MX AIPSTZ driver, i.MX95 pinctrl driver, Ethernet and PCIe support in arm64 defconfig * tag 'imx-defconfig-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: defconfig: enable i.MX AIPSTZ driver ARM: mxs_defconfig: enable sound drivers for imx28-amarula-rmm arm64: defconfig: Enable i.MX95 drivers for pinctrl, Ethernet and PCIe Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'tegra-for-6.19-arm64-defconfig' of ↵Arnd Bergmann1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig arm64: tegra: Default configuration changes for v6.19-rc1 Enable the new driver for the VRS PSEQ RTC found on Tegra234 and later. * tag 'tegra-for-6.19-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: defconfig: Enable NVIDIA VRS PSEQ RTC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'tegra-for-6.19-arm-defconfig' of ↵Arnd Bergmann1-4/+0
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig ARM: tegra: Default configuration changes for v6.19-rc1 Enable ext4 by default on Tegra to restore systems booting from MMC. * tag 'tegra-for-6.19-arm-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Enable EXT4 for Tegra Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'mtk-defconfig-for-v6.19' of ↵Arnd Bergmann1-0/+1
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig MediaTek defconfig updates As MediaTek boards with UFS appeared some time ago, this adds a single commit enabling the MediaTek UFS driver, allowing those boards to boot over UFS as primary storage. * tag 'mtk-defconfig-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: arm64: defconfig: Enable UFS support for MediaTek Genio 1200 EVK UFS board Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21arm64: defconfig: enable Exynos ACPM clocksTudor Ambarus1-0/+1
Enable the Exynos ACPM clocks driver. Samsung Exynos platforms implement ACPM to provide support for clock configuration, PMIC and temperature sensors. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole Link: https://patch.msgid.link/20251010-acpm-clk-v6-5-321ee8826fd4@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251110121344.120785-5-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'renesas-arm-defconfig-for-v6.19-tag1' of ↵Arnd Bergmann2-1/+6
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig Renesas ARM defconfig updates for v6.19 - Enable support for the Renesas RZ/G3S and RZ/G3E thermal drivers, and the RZ/T2H and RZ/N2H ADC drivers in the ARM64 defconfig, - Refresh the ARM SH-Mobile defconfig for v6.18-rc1. * tag 'renesas-arm-defconfig-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: defconfig: Enable RZ/T2H / RZ/N2H ADC driver ARM: shmobile: defconfig: Refresh for v6.18-rc1 arm64: defconfig: Enable the Renesas RZ/G3E thermal driver arm64: defconfig: Enable Renesas RZ/G3S thermal driver Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21arm64: defconfig: Remove the redundant SCHED_MC/SCHED_SMTHuang Shijie1-2/+0
The patch "7bd291abe2d sched: Unify the SCHED_{SMT,CLUSTER,MC} Kconfig" has enabled the SCHED_MC/SCHED_SMT by default for arm64. So remove the redundant code in defconfig. Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com> Link: https://lore.kernel.org/r/20251021075704.527626-1-shijie@os.amperecomputing.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'anlogic-initial-6.19-v2' of ↵Arnd Bergmann6-0/+137
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/newsoc Initial Anlogic Platform Support Add bindings for the serial and timer peripherals, and a basic soc dtsi for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board for this SoC. Add myself as maintainer for this platform for the time being. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: MAINTAINERS: Setup support for Anlogic tree riscv: defconfig: Enable Anlogic SoC riscv: dts: anlogic: Add Milianke MLKPAI FS01 board riscv: dts: Add initial Anlogic DR1V90 SoC device tree riscv: Add Anlogic SoC famly Kconfig support dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER dt-bindings: riscv: Add Anlogic DR1V90 dt-bindings: riscv: Add Nuclei UX900 compatibles dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
2025-11-21Merge tag 'imx-fixes-6.18-2' of ↵Arnd Bergmann4-5/+10
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.18, 2nd round: - Correct i.MX8DXL's pcie-ep interrupt number (Frank Li) - Swap interrupt numbers of eqos for imx8dxl-ss-conn (Frank Li) - Correct SAI3 interrupt line for i.MX6UL (Maarten Zanders) - Correct mux-controller select/enable-gpios polarity for imx8qm-mek board (Xu Yang) * tag 'imx-fixes-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8qm-mek: fix mux-controller select/enable-gpios polarity ARM: dts: nxp: imx6ul: correct SAI3 interrupt line arm64: dts: imx8dxl-ss-conn: swap interrupts number of eqos arm64: dts: imx8dxl: Correct pcie-ep interrupt number Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21ARM: versatile: Fix typo in versatile.cShivam Chaudhary1-1/+1
Corrected minor typo in versatile.c - Fixed "documentaton" to "documentation" Signed-off-by: Shivam Chaudhary <cvam0000@gmail.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20251023223258.3181274-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'mtk-arm32-for-v6.19' of ↵Arnd Bergmann3-0/+6
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/arm MediaTek mach ARM32 updates This adds support for the MT6582 SoC and its SMP bringup code. This SoC is found in old smartphones and tablets from various manufacturers. * tag 'mtk-arm32-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: ARM: mediatek: add MT6582 smp bring up code ARM: mediatek: add board_dt_compat entry for the MT6582 SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge branch 'bst/newsoc' into soc/newsocArnd Bergmann6-0/+133
This patch series introduces platform support for Black Sesame Technologies (BST) C1200 SoC and CDCU1.0 ADAS 4C2G board. BST is a leading automotive-grade computing SoC provider focusing on intelligent driving, computer vision, and AI capabilities for ADAS and autonomous driving applications. You can find more information about the SoC and related boards at: https://bst.ai This series provides the foundational platform enablement including device tree bindings, SoC and board device trees, platform configuration, and maintainer information. MMC/SDHCI driver support will be submitted in a separate patch series. * bst/newsoc: MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support arm64: defconfig: enable BST platform support arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs dt-bindings: arm: add Black Sesame Technologies (bst) SoC dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd. Link: https://lore.kernel.org/all/20251016120558.2390960-1-yangzh0906@thundersoft.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21arm64: defconfig: enable BST platform supportAlbert Yang1-0/+1
Enable support for Black Sesame Technologies (BST) platform in the ARM64 defconfig: - CONFIG_ARCH_BST: Enable BST SoC platform support Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 boardAlbert Yang4-0/+124
Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, and interrupt controller. Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCsAlbert Yang1-0/+8
Add ARCH_BST configuration option to enable support for Black Sesame Technologies SoC family. BST produces automotive-grade system-on-chips for intelligent driving, focusing on computer vision and AI capabilities. The BST C1200 family includes SoCs for ADAS and autonomous driving applications. Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'ti-k3-dt-for-v6.19-part2' of ↵Arnd Bergmann3-7/+41
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt TI K3 device tree updates for v6.19 part2 Late fixes and cleanups: * Fix build warnings for unapplied overlays for PHYTEC, SA67 and certain TI EVM * Fix pinmux of SD regulator control line on J721e SK * Correct unit address of cbass_wakeup node for AM62L * tag 'ti-k3-dt-for-v6.19-part2' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: arm64: dts: ti: k3-am62l: Fix unit address of cbass_wakeup arm64: dts: ti: k3-j721e-sk: Fix pinmux for pin Y1 used by power regulator arm64: dts: ti: Add missing applied DT overlay targets arm64: dts: ti: sa67: add build time dtb for overlays arm64: dts: ti: Enable build testing of PHYTEC board overlays Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'mvebu-dt64-6.19-1' of ↵Arnd Bergmann6-19/+7
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt mvebu dt64 for 6.19 (part 1) pinctrl node names cleanup from Rob on Marvell device tree files Proper fix for pci errors on armada cp11x based platforms * tag 'mvebu-dt64-6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: clk: mvebu: cp110 add CLK_IGNORE_UNUSED to pcie_x10, pcie_x11 & pcie_x4 Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports" arm64/arm: dts: marvell: Rename "nand-rb" pinctrl node names Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'riscv-sophgo-dt-for-v6.19' of https://github.com/sophgo/linux ↵Arnd Bergmann8-0/+265
into soc/dt RISC-V Devicetrees for v6.19 Sophgo: For CV18xx serials: Add top syscon device related DTS change, the top system controller provides register access to configure some misc modules, such as usb2 phy and a dma multiplexer. For SG2042: There are two changes. The first one is to add DTS definition for PCIe controllers for SoC SG2042 and boards such as Pioneerbox/EVB_V1/EVB_V2 uses SG2042. The second one is to add DTS to support SPI-NOR flash controllers for this SoC and the same for related boards. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.19' of https://github.com/sophgo/linux: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 riscv: dts: sophgo: Enable SPI NOR node for PioneerBox riscv: dts: sophgo: Add SPI NOR node for SG2042 riscv: dts: sophgo: Add USB support for cv18xx riscv: dts: sophgo: Add syscon node for cv18xx dt-bindings: soc: sophgo: add TOP syscon for CV18XX/SG200X series SoC riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X riscv: sophgo: dts: enable PCIe for PioneerBox riscv: sophgo: dts: add PCIe controllers for SG2042 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'cix-dt-v6.19-rc1' of ↵Arnd Bergmann3-0/+609
git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt CIX device tree changes for v6.19-rc1, add below new components support: - PCIe - Pinctrl - SPI * tag 'cix-dt-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix: arm64: dts: cix: add a compatible string for the cix sky1 SoC arm64: dts: cix: Enable PCIe on the Orion O6 board arm64: dts: cix: Add PCIe Root Complex on sky1 arm64: dts: cix: Add pinctrl nodes for sky1 arm64: dts: cix: add DT nodes for SPI Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'stm32-dt-for-v6.19-1' of ↵Arnd Bergmann8-11/+34
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.19, round 1 Highlights: ----------- - MPU: - STM32MP13: - Add and enable the ARM SMC watchdog to use IWDG1 in the secure world. - STMP32MP15: - Phytec SOM: Fix STMPE811 touchscreen - LXA: drop unnecessary vusb_d/a-supply as already defined by "phy-supply" and "vdda1v8-supply". - STM32MP23: - Use the RIFSC as an access controler (firewall) as it is done for STM32MP25 and STM32MP23. - STM32MP25: - Add OSPI memory region name. - Add I/O synchronization properties to satisfy RGMII specification. * tag 'stm32-dt-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: arm64: dts: st: set RIFSC as an access controller on stm32mp21x platforms ARM: dts: stm32: add the IWDG2 interrupt line in stm32mp131.dtsi ARM: dts: stm32: enable the ARM SMC watchdog node in stm32mp135f-dk ARM: dts: stm32: add the ARM SMC watchdog in stm32mp131.dtsi ARM: dts: stm32: add iwdg1 node in stm32mp131.dtsi arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsi arm64: dts: st: Add memory-region-names property for stm32mp257f-ev1 ARM: dts: stm32: lxa: drop unnecessary vusb_d/a-supply ARM: dts: stm32: stm32mp157c-phycore: Fix STMPE811 touchscreen node properties Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'v6.19-rockchip-dts64-1' of ↵Arnd Bergmann25-36/+3572
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards: 9Tripod X3568, 100ASK DShanPi A1, LinkEase EasePi R1, FriendlyElec NanoPi R76S Interesting archeological addition: RK3368 (2015) gets display output afterall. New peripherals: vicap on px30 and rk356x, PCIe Gen2x1 on RK3528, use actual clock-ids for SCMI clocks - not hardcoded numbers, CQE support for the eMMC on RK3588. As well as a number of enablements for individual boards. For example enablement for the now usable NPU. * tag 'v6.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (43 commits) arm64: dts: rockchip: add vicap node to rk356x arm64: dts: rockchip: add the vip node to px30 arm64: dts: rockchip: fixes audio for 100ASK DshanPi A1 arm64: dts: rockchip: fixes vcc3v3_s0 supply for 100ASK DshanPi A1 arm64: dts: rockchip: fixes ethernet for 100ASK DshanPi A1 arm64: dts: rockchip: fixes regulator for 100ASK DshanPi A1 arm64: dts: rockchip: correct assigned-clock-rates spelling on 2 boards arm64: dts: rockchip: clean up devicetree for 9Tripod X3568 v4 arm64: dts: rockchip: Enable USB-C DP Alt for Indiedroid Nova arm64: dts: rockchip: add eMMC CQE support for rk3588 arm64: dts: rockchip: enable HDMI audio on Rock 5 ITX arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 3C arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 5A arm64: dts: rockchip: Move the EEPROM to correct I2C bus on Radxa ROCK 5A arm64: dts: rockchip: use SCMI clock id for gpu clock on rk356x arm64: dts: rockchip: Remove sdmmc max-frequency on RK3588S EVB1 board arm64: dts: rockchip: Remove sdmmc max-frequency for Radxa ROCK 5 ITX/5B/5B+/5T arm64: dts: rockchip: Switch microSD card detect to gpio on Radxa ROCK 5 ITX/5C arm64: dts: rockchip: Add devicetree for the 9Tripod X3568 v4 dt-bindings: arm: rockchip: Add 9Tripod X3568 series ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-29 01:26:44 +0300