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2026-01-05arm64: dts: renesas: r9a09g077: Add DMAC supportCosmin Tanislav1-0/+90
The Renesas RZ/T2H (R9A09G077) SoC has three instances of the DMAC IP. Add support for them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205151254.2970669-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g087: Add ICU supportCosmin Tanislav1-0/+73
The Renesas RZ/N2H (R9A09G087) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251201112933.488801-5-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g077: Add ICU supportCosmin Tanislav1-0/+73
The Renesas RZ/T2H (R9A09G077) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251201112933.488801-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g047e57-smarc: Enable rsci{2,4,9} nodesBiju Das3-0/+69
Enable device rsci{2,4,9} nodes for the RZ/G3E SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251129185203.380002-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: renesas-smarc2: Move aliases to board DTSBiju Das2-6/+6
SMARC2 board dtsi is common for multiple SoCs. So Move aliases to board DTS as SoC may have different IPs for a given alias. eg: RZ/G3S does not have RSCI interface. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20251129185203.380002-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g047: Add RSCI nodesBiju Das1-0/+220
Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251129185203.380002-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05ARM: dts: renesas: r9a06g032: Add Ethernet switch interruptsGeert Uytterhoeven1-0/+6
The Ethernet switch device node still lacks interrupts. Add them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/53d45eed3709cba589a4ef3e9ad198d7e44fd9a5.1764249063.git.geert+renesas@glider.be
2026-01-05arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button supportLad Prabhakar1-0/+13
Add support for the NMI connected user pushbutton on the RZ/V2N EVK. The button is wired to the SoC NMI input and can be used to wake the system from low-power states. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add RSPI nodesLad Prabhakar1-0/+63
Add nodes for the RSPI IPs found in the Renesas RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add DMAC nodesLad Prabhakar1-0/+165
Add nodes for the DMAC IPs found on the Renesas RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add ICU nodeLad Prabhakar1-0/+92
Add node for the Interrupt Control Unit IP found on the Renesas RZ/V2N SoC, and modify the pinctrl node as its interrupt parent is the ICU node. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g047e57-smarc: Remove duplicate SW_LCD_ENGeert Uytterhoeven1-1/+0
SW_LCD_EN is defined twice. Fixes: 9e95446b0cf93a91 ("arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/1f93558c62f4461f50935644ec831a7d2cb52630.1764089463.git.geert+renesas@glider.be
2026-01-05arm64: dts: renesas: r9a09g087: Add SPI nodesCosmin Tanislav1-0/+72
Add support for the four SPI controllers on the Renesas RZ/N2H Soc. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119161434.595677-14-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g077: Add SPI nodesCosmin Tanislav1-0/+72
Add support for the four SPI controllers on the Renesas RZ/T2H Soc. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119161434.595677-13-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: rzg3s-smarc: Enable PCIeClaudiu Beznea1-0/+11
The RZ Smarc Carrier-II board has PCIe headers mounted on it. Enable PCIe support. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251119143523.977085-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clockClaudiu Beznea1-0/+5
Versa3 clock generator available on RZ/G3S SMARC Module provides the reference clock for SoC PCIe interface. Update the device tree to reflect this connection. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251119143523.977085-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a08g045: Add PCIe nodeClaudiu Beznea1-0/+65
The RZ/G3S SoC has a variant (R9A08G045S33) which supports PCIe. Add the PCIe node. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251119143523.977085-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB3.0 PHY and xHCI ↵Lad Prabhakar1-0/+15
controller Enable the USB3.0 (CH0) host controllers on the RZ/V2N Evaluation Kit. The CN4 connector on the EVK provides access to the USB3.0 channel. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119110505.100253-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add USB3 PHY/Host nodesLad Prabhakar1-0/+30
Add USB3 PHY/Host nodes to RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119110505.100253-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB3.0 PHYs and xHCI ↵Lad Prabhakar1-0/+30
controllers Enable the USB3.0 (CH0) and USB3.1 (CH1) host controllers on the RZ/V2H Evaluation Kit. The CN4 stacked connector on the EVK provides access to both channels, with CH0 corresponding to USB3.0 and CH1 to USB3.1. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119110505.100253-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g057: Add USB3 PHY/Host nodesLad Prabhakar1-0/+60
Add USB3 PHY/Host nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119110505.100253-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable DU and DSILad Prabhakar1-0/+69
Enable DU, DSI and adv7535 HDMI encoder on RZ/V2N Evaluation Kit. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251103200349.62087-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add DU and DSI nodesLad Prabhakar1-0/+65
Add DU and DSI nodes to RZ/V2N SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251103200349.62087-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g056: Add FCPV and VSPD nodesLad Prabhakar1-0/+24
Add FCPV and VSPD nodes to RZ/V2N SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251103200349.62087-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g057h48-kakip: Enable SPI NOR FlashNobuhiro Iwamatsu1-0/+39
This enables W25Q256JWPIM NOR Flash connected to XSPI. Additionally, this adds fixed 1.8V regulator node (`reg_1p8v`) required for NOR Flash. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251101072951.2681630-1-iwamatsu@nigauri.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable DU and DSILad Prabhakar1-0/+71
Enable DU, DSI and adv7535 HDMI encoder on RZ/V2H Evaluation Kit. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023212314.679303-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g057: Add DU and DSI nodesLad Prabhakar1-0/+65
Add DU and DSI nodes to RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023212314.679303-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: r9a09g057: Add FCPV and VSPD nodesLad Prabhakar1-0/+24
Add FCPV and VSPD nodes to RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023212314.679303-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05arm64: dts: renesas: rzt2h-n2h-evk: Add note about SD1 1.8V modesCosmin Tanislav2-0/+6
1.8V operation of SD1 requires the jumper to be placed on the correct pins of a connector on these Evaluation Kits. 1.8V is needed to achieve the higher rated speeds like SDR104. Add a note about it to make sure no one else spends too much time figuring this out. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251022073141.1989762-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-05x86,fs/resctrl: Rename some L3 specific functionsTony Luck3-11/+13
With the arrival of monitor events tied to new domains associated with a different resource it would be clearer if the L3 resource specific functions are more accurately named. Rename three groups of functions: Functions that allocate/free architecture per-RMID MBM state information: arch_domain_mbm_alloc() -> l3_mon_domain_mbm_alloc() mon_domain_free() -> l3_mon_domain_free() Functions that allocate/free filesystem per-RMID MBM state information: domain_setup_mon_state() -> domain_setup_l3_mon_state() domain_destroy_mon_state() -> domain_destroy_l3_mon_state() Initialization/exit: rdt_get_mon_l3_config() -> rdt_get_l3_mon_config() resctrl_mon_resource_init() -> resctrl_l3_mon_resource_init() resctrl_mon_resource_exit() -> resctrl_l3_mon_resource_exit() Ensure kernel-doc descriptions of these functions' return values are present and correctly formatted. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/20251217172121.12030-1-tony.luck@intel.com
2026-01-05x86,fs/resctrl: Rename struct rdt_mon_domain and rdt_hw_mon_domainTony Luck3-33/+33
The upcoming telemetry event monitoring is not tied to the L3 resource and will have a new domain structure. Rename the L3 resource specific domain data structures to include "l3_" in their names to avoid confusion between the different resource specific domain structures: rdt_mon_domain -> rdt_l3_mon_domain rdt_hw_mon_domain -> rdt_hw_l3_mon_domain No functional change. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/20251217172121.12030-1-tony.luck@intel.com
2026-01-05x86,fs/resctrl: Use struct rdt_domain_hdr when reading countersTony Luck1-3/+9
Convert the whole call sequence from mon_event_read() to resctrl_arch_rmid_read() to pass resource independent struct rdt_domain_hdr instead of an L3 specific domain structure to prepare for monitoring events in other resources. This additional layer of indirection obscures which aspects of event counting depend on a valid domain. Event initialization, support for assignable counters, and normal event counting implicitly depend on a valid domain while summing of domains does not. Split summing domains from the core event counting handling to make their respective dependencies obvious. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/20251217172121.12030-1-tony.luck@intel.com
2026-01-05x86/sev: Disable GCOV on noinstr objectBrendan Jackman1-0/+2
With Debian clang version 19.1.7 (3+build5) there are calls to kasan_check_write() from __sev_es_nmi_complete(), which violates noinstr. Fix it by disabling GCOV for the noinstr object, as has been done for previous such instrumentation issues. Note that this file already disables __SANITIZE_ADDRESS__ and __SANITIZE_THREAD__, thus calls like kasan_check_write() ought to be nops regardless of GCOV. This has been fixed in other patches. However, to avoid any other accidental instrumentation showing up, (and since, in principle GCOV is instrumentation and hence should be disabled for noinstr code anyway), disable GCOV overall as well. Signed-off-by: Brendan Jackman <jackmanb@google.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Marco Elver <elver@google.com> Link: https://patch.msgid.link/20251216-gcov-inline-noinstr-v3-3-10244d154451@google.com
2026-01-04x86/split_lock: Remove dead string when split_lock_detect=fatalRong Zhang1-6/+3
sld_state_show() has a dead str1 below: if (A) { ... } else if (B) { pr_info(... A ? str1 : str2 ...); } where A is always false in the second block, implied by the "if (A) else" pattern. Hence, str2 is always used. This seems to be some mysterious legacy inherited from the earlier patch revisions of ebb1064e7c2e ("x86/traps: Handle #DB for bus lock"). Earlier revisions¹ did enable both sld and bld at the same time to detect non-WB bus_locks when split_lock_detect=fatal, but that's no longer true in the merged revision. Remove it and translate the pr_info() into its equivalent form. ¹ https://lore.kernel.org/r/20201121023624.3604415-3-fenghua.yu@intel.com [ bp: Massage commit message; simplify braces ] Signed-off-by: Rong Zhang <i@rong.moe> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20251215182907.152881-1-i@rong.moe
2026-01-04x86,fs/resctrl: Refactor domain create/remove using struct rdt_domain_hdrTony Luck1-2/+2
Up until now, all monitoring events were associated with the L3 resource and it made sense to use the L3 specific "struct rdt_mon_domain *" argument to functions operating on domains. Telemetry events will be tied to a new resource with its instances represented by a new domain structure that, just like struct rdt_mon_domain, starts with the generic struct rdt_domain_hdr. Prepare to support domains belonging to different resources by changing the calling convention of functions operating on domains. Pass the generic header and use that to find the domain specific structure where needed. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/20251217172121.12030-1-tony.luck@intel.com
2026-01-04x86/resctrl: Clean up domain_remove_cpu_ctrl()Tony Luck1-15/+14
For symmetry with domain_remove_cpu_mon() refactor domain_remove_cpu_ctrl() to take an early return when removing a CPU does not empty the domain. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/20251217172121.12030-1-tony.luck@intel.com
2026-01-04x86/resctrl: Refactor domain_remove_cpu_mon() ready for new domain typesTony Luck1-10/+17
New telemetry events will be associated with a new package scoped resource with a new domain structure. Refactor domain_remove_cpu_mon() so all the L3 domain processing is separate from the general domain action of clearing the CPU bit in the mask. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/20251217172121.12030-1-tony.luck@intel.com
2026-01-04x86/resctrl: Move L3 initialization into new helper functionTony Luck1-30/+34
Carve out the resource monitoring domain init code into a separate helper in order to be able to initialize new types of monitoring domains besides the usual L3 ones. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/20251217172121.12030-1-tony.luck@intel.com
2026-01-04x86,fs/resctrl: Improve domain type checkingTony Luck1-4/+6
Every resctrl resource has a list of domain structures. struct rdt_ctrl_domain and struct rdt_mon_domain both begin with struct rdt_domain_hdr with rdt_domain_hdr::type used in validity checks before accessing the domain of a particular type. Add the resource id to struct rdt_domain_hdr in preparation for a new monitoring domain structure that will be associated with a new monitoring resource. Improve existing domain validity checks with a new helper domain_header_is_valid() that checks both domain type and resource id. domain_header_is_valid() should be used before every call to container_of() that accesses a domain structure. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/20251217172121.12030-1-tony.luck@intel.com
2026-01-03arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocksAbel Vesa1-2/+2
It seems the USB combo SS1 and SS2 ref clocks have another gate, unlike the SS0. These gates are part of the TCSR clock controller. At least on Dell XPS 13 (9345), if the ref clock provided by the TCSR clock controller for SS1 PHY is disabled on the clk_disable_unused late initcall, the PHY fails to initialize. It doesn't happen on the SS0 PHY and the SS2 is not used on this device. This doesn't seem to be a problem on CRD though. It might be that the RPMh has a vote for it from some other consumer and does not actually disable it when ther kernel drops its vote. Either way, these TCSR provided clocks seem to be the correct ones for the SS1 and SS2, so use them instead. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: qcs8300: Add support for camssVikram Sharma1-0/+172
Add changes to support the camera subsystem on the QCS8300. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251107162521.511536-3-quic_vikramsa@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: sdm630: Add FastRPC nodes to ADSPNickolay Goppen1-0/+33
Add FastRPC subnode with compute-cb subnodes to ADSP node. Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Link: https://lore.kernel.org/r/20251110-qcom-sdm660-cdsp-adsp-dts-v3-3-d1f1c86e2e6d@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: sdm630: Add missing vote clock and GDSC to lpass_smmuNickolay Goppen1-0/+5
Add missing vote clock and GDSC to lpass_smmu node to make sure the required resources are enabled before attempting to access the hardware. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Link: https://lore.kernel.org/r/20251110-qcom-sdm660-cdsp-adsp-dts-v3-2-d1f1c86e2e6d@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: sdm630/660: Add CDSP-related nodesNickolay Goppen3-10/+176
In order to enable CDSP support for SDM660 SoC: * add shared memory p2p nodes for CDSP * add CDSP-specific smmu node * add CDSP peripheral image loader node Memory region for CDSP in SDM660 occupies the same spot as TZ buffer mem defined in sdm630.dtsi (which does not have CDSP). In sdm660.dtsi replace buffer_mem inherited from SDM630 with cdsp_region, which is also larger in size. SDM636 also doesn't have CDSP, so remove inherited from sdm660.dtsi related nodes and add buffer_mem back. Signed-off-by: Nickolay Goppen <setotau@mainlining.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251110-qcom-sdm660-cdsp-adsp-dts-v3-1-d1f1c86e2e6d@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: hamoa-iot-evk: Add backlight support for eDP panelYongxing Mou1-0/+54
The backlight on the Hamoa IoT EVK is controlled through a PWM signal. Aligned with other x1e80100-based platforms: the PWM signal is controlled by PMK8550, and the backlight enable signal is handled by PMC8380. Describe the backlight device and connect it to the eDP panel to allow for brightness control. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251112-hamoa_dvt_backlight-v3-1-f35b44af7fc4@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: hamoa-iot-evk: enable PWM RG LEDsTingguo Cheng1-0/+23
Add RED and GREEN LED channels for the RGB device connected to PMC8380C PWM-LED pins. Omit BLUE channel to match default hardware setup where it's tied to EDL indicator. Signed-off-by: Tingguo Cheng <tingguo.cheng@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251114-add-rgb-led-for-hamoa-iot-evk-v3-1-5df1fcd68374@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: msm8937: add reset for display subsystemBarnabás Czémán1-0/+1
Add reset for display subsystem. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251117-mdss-resets-msm8917-msm8937-v2-4-a7e9bbdaac96@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: msm8917: add reset for display subsystemBarnabás Czémán1-1/+1
Add reset for display subsystem. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251117-mdss-resets-msm8917-msm8937-v2-3-a7e9bbdaac96@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: sdm845-oneplus: Mark l14a regulator as boot-onCasey Connolly1-0/+1
This regulator is used only for the display, which is enabled by the bootloader and left on for continuous splash. Mark it as such. Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices") Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-dts-oneplus-regulators-v2-3-3e67cea1e4e7@ixit.cz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: sdm845-oneplus: Don't keep panel regulator always onCasey Connolly1-1/+0
The panel regulator doesn't need to be always on, so remove this property. Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices") Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-dts-oneplus-regulators-v2-2-3e67cea1e4e7@ixit.cz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-26 07:03:41 +0300