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2026-01-30pseries/plpks: fix kernel-doc comment inconsistenciesSrish Srinivasan2-87/+318
Fix issues with comments for all the applicable functions to be consistent with kernel-doc format. Move them before the function definition as opposed to the function prototype. Signed-off-by: Srish Srinivasan <ssrish@linux.ibm.com> Tested-by: Nayna Jain <nayna@linux.ibm.com> Reviewed-by: Nayna Jain <nayna@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260127145228.48320-2-ssrish@linux.ibm.com
2026-01-30Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski29-86/+151
Cross-merge networking fixes after downstream PR (net-6.19-rc8). No adjacent changes, conflicts: drivers/net/ethernet/spacemit/k1_emac.c 2c84959167d64 ("net: spacemit: Check for netif_carrier_ok() in emac_stats_update()") f66086798f91f ("net: spacemit: Remove broken flow control support") https://lore.kernel.org/aXjAqZA3iEWD_DGM@sirena.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-29Merge tag 'mm-hotfixes-stable-2026-01-29-09-41' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm Pull misc fixes from Andrew Morton: "16 hotfixes. 9 are cc:stable, 12 are for MM. There's a patch series from Pratyush Yadav which fixes a few things in the new-in-6.19 LUO memfd code. Plus the usual shower of singletons - please see the changelogs for details" * tag 'mm-hotfixes-stable-2026-01-29-09-41' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm: vmcoreinfo: make hwerr_data visible for debugging mm/zone_device: reinitialize large zone device private folios mm/mm_init: don't cond_resched() in deferred_init_memmap_chunk() if called from deferred_grow_zone() mm/kfence: randomize the freelist on initialization kho: kho_preserve_vmalloc(): don't return 0 when ENOMEM kho: init alloc tags when restoring pages from reserved memory mm: memfd_luo: restore and free memfd_luo_ser on failure mm: memfd_luo: use memfd_alloc_file() instead of shmem_file_setup() memfd: export alloc_file() flex_proportions: make fprop_new_period() hardirq safe mailmap: add entry for Viacheslav Bocharov mm/memory-failure: teach kill_accessing_process to accept hugetlb tail page pfn mm/memory-failure: fix missing ->mf_stats count in hugetlb poison mm, swap: restore swap_space attr aviod kernel panic mm/kasan: fix KASAN poisoning in vrealloc() mm/shmem, swap: fix race of truncate and swap entry split
2026-01-29Merge branch 'for-next/misc' into for-next/coreWill Deacon4-6/+8
* for-next/misc: arm64: mm: warn once for ioremap attempts on RAM mappings arm64: Disable branch profiling for all arm64 code arm64: kernel: initialize missing kexec_buf->random field arm64: simplify arch_uprobe_xol_was_trapped return
2026-01-29Merge branch 'for-next/errata' into for-next/coreWill Deacon4-0/+61
* for-next/errata: arm64: errata: Workaround for SI L1 downstream coherency issue
2026-01-29Merge branch 'for-next/entry' into for-next/coreWill Deacon5-28/+46
* for-next/entry: arm64/ptrace: Return early for ptrace_report_syscall_entry() error arm64/ptrace: Split report_syscall() arm64: Remove unused _TIF_WORK_MASK arm64: Avoid memcpy() for syscall_get_arguments() syscall.h: Remove unused SYSCALL_MAX_ARGS
2026-01-29Merge branch 'for-next/cpufreq' into for-next/coreWill Deacon1-3/+63
* for-next/cpufreq: arm64: topology: Do not warn on missing AMU in cpuhp_topology_online() arm64: topology: Handle AMU FIE setup on CPU hotplug cpufreq: Add new helper function returning cpufreq policy arm64: topology: Skip already covered CPUs when setting freq source
2026-01-29Merge tag 'ti-k3-dt-for-v6.20' of ↵Arnd Bergmann35-160/+238
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt TI K3 device tree updates for v6.20 Generic Fixes/Cleanups: - Minor whitespace cleanup and lowercase hex formatting for consistency - Various DT schema warning fixes across multiple boards SoC Specific Features and Fixes: AM62P/J722S: - Add HSM M4F node for hardware security module support J784S4/J742S2/J721S2: - Add HSM M4F node for hardware security module support - Refactor watchdog instances for j784s4 - Move c71_3 node to appropriate order in device tree Board Specific Fixes: AM62: - phycore-som: Add bootphase tags to cpsw_mac_syscon and phy_gmii_sel AM62A: - phycore-som: Add bootphase tags to cpsw_mac_syscon and phy_gmii_sel AM62P: - Verdin: Fix SD regulator startup delay AM67A: - Kontron SA67: Fix CMA node and SD card regulator configuration AM69: - Aquila: Change main_spi0/2 chip select to GPIO mode - Aquila-clover: Change main_spi2 CS0 to GPIO mode - Aquila-dev/clover: Fix USB-C Sink PDO configuration * tag 'ti-k3-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix SD card regulator arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix CMA node arm64: dts: ti: k3-am62p-j722s-common-main: Add HSM M4F node arm64: dts: ti: k3-{j784s4-j742s2/j721s2}-mcu-wakeup: Add HSM M4F node arm64: dts: ti: k3-j784s4-j742s2-main-common.dtsi: Refactor watchdog instances for j784s4 arm64: dts: ti: k3-j784s4-main.dtsi: Move c71_3 node to appropriate order arm64: dts: ti: k3-am69-aquila-clover: Change main_spi2 CS0 to GPIO mode arm64: dts: ti: k3-am69-aquila: Change main_spi0/2 CS to GPIO mode arm64: dts: ti: Use lowercase hex arm64: dts: ti: Minor whitespace cleanup arm64: dts: ti: am62p-verdin: Fix SD regulator startup delay arm64: dts: ti: k3-am69-aquila-clover: Fix USB-C Sink PDO arm64: dts: ti: k3-am69-aquila-dev: Fix USB-C Sink PDO arm64: dts: ti: k3-am62(a)-phycore-som: Add bootphase tag to phy_gmii_sel arm64: dts: ti: k3-am62a-phycore-som: Add bootphase tag to cpsw_mac_syscon arm64: dts: ti: k3-am62-phycore-som: Add bootphase tag to cpsw_mac_syscon arm64: dts: ti: k3-am62-lp-sk-nand: Rename pinctrls to fix schema warnings arm64: dts: ti: k3-am642-phyboard-electra-x27-gpio1-spi1-uart3: Fix schema warnings arm64: dts: ti: k3-am642-phyboard-electra-peb-c-010: Fix icssg-prueth schema warning Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29riscv: ptrace: return ENODATA for inactive vector extensionIlya Mamay1-2/+8
Currently, ptrace returns EINVAL when the vector extension is supported but not yet activated for the traced process. This error code is not always appropriate since the ptrace arguments may be valid. Debug tools like gdbserver expect ENODATA when the requested register set is not active, e.g. see [1]. This expectation seems to be more appropriate, so modify the vector ptrace implementation to return: - EINVAL when V extension is not supported - ENODATA when V extension is supported but not active [1] https://github.com/bminor/binutils-gdb/blob/637f25e88675fa47e47f9cc5e2cf37384836b8a2/gdbserver/linux-low.cc#L5020 Signed-off-by: Ilya Mamay <mmamayka01@gmail.com> Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Reviewed-by: Andy Chiu <andybnac@gmail.com> Tested-by: Andy Chiu <andybnac@gmail.com> Link: https://patch.msgid.link/20251214163537.1054292-2-geomatsi@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv: create a Kconfig fragment for shadow stack and landing pad supportDeepak Gupta2-0/+26
This patch creates a Kconfig fragment for shadow stack support and landing pad instruction support. Shadow stack support and landing pad instruction support can be enabled by selecting 'CONFIG_RISCV_USER_CFI'. Selecting 'CONFIG_RISCV_USER_CFI' wires up the path to enumerate CPU support. If support exists, the kernel will support CPU-assisted user mode CFI. If CONFIG_RISCV_USER_CFI is selected, select 'ARCH_USES_HIGH_VMA_FLAGS', 'ARCH_HAS_USER_SHADOW_STACK' and 'DYNAMIC_SIGFRAME' for riscv. Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-25-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned up patch description, Kconfig text; added CONFIG_MMU exclusion] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29arch/riscv: add dual vdso creation logic and select vdso based on hwDeepak Gupta8-11/+82
Shadow stack instructions are taken from the Zimop ISA extension, which is mandated on RVA23. Any userspace with shadow stack instructions in it will fault on hardware that doesn't have support for Zimop. Thus, a shadow stack-enabled userspace can't be run on hardware that doesn't support Zimop. It's not known how Linux userspace providers will respond to this kind of binary fragmentation. In order to keep kernel portable across different hardware, 'arch/riscv/kernel/vdso_cfi' is created which has Makefile logic to compile 'arch/riscv/kernel/vdso' sources with CFI flags, and 'arch/riscv/kernel/vdso.c' is modified to select the appropriate vdso depending on whether the underlying CPU implements the Zimop extension. Since the offset of vdso symbols will change due to having two different vdso binaries, there is added logic to include a new generated vdso offset header and dynamically select the offset (like for rt_sigreturn). Signed-off-by: Deepak Gupta <debug@rivosinc.com> Acked-by: Charles Mirabile <cmirabil@redhat.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-24-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned up patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29arch/riscv: compile vdso with landing pad and shadow stack noteJim Shu9-3/+81
User mode tasks compiled with Zicfilp may call indirectly into the vdso (like hwprobe indirect calls). Add support for compiling landing pads into the vdso. Landing pad instructions in the vdso will be no-ops for tasks which have not enabled landing pads. Furthermore, add support for the C sources of the vdso to be compiled with shadow stack and landing pads enabled as well. Landing pad and shadow stack instructions are emitted only when the VDSO_CFI cflags option is defined during compile. Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-23-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned up patch description, issues reported by checkpatch] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv: enable kernel access to shadow stack memory via the FWFT SBI callDeepak Gupta2-0/+33
The kernel has to perform shadow stack operations on the user shadow stack. During signal delivery and sigreturn, the shadow stack token must be created and validated respectively. Thus shadow stack access for the kernel must be enabled. In the future, when kernel shadow stacks are enabled, they must be enabled as early as possible for better coverage and to prevent any imbalance between the regular stack and the shadow stack. After 'relocate_enable_mmu' has completed, this is the earliest that it can be enabled. Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-22-b55691eacf4f@rivosinc.com [pjw@kernel.org: updated to apply; cleaned up commit message] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv: add kernel command line option to opt out of user CFIDeepak Gupta3-13/+61
Add a kernel command line option to disable part or all of user CFI. User backward CFI and forward CFI can be controlled independently. The kernel command line parameter "riscv_nousercfi" can take the following values: - "all" : Disable forward and backward cfi both - "bcfi" : Disable backward cfi - "fcfi" : Disable forward cfi Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-21-b55691eacf4f@rivosinc.com [pjw@kernel.org: fixed warnings from checkpatch; cleaned up patch description, doc, printk text] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv/hwprobe: add zicfilp / zicfiss enumeration in hwprobeDeepak Gupta2-2/+6
Add enumeration of the zicfilp and zicfiss extensions in the hwprobe syscall. Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-20-b55691eacf4f@rivosinc.com [pjw@kernel.org: updated to apply; extend into RISCV_HWPROBE_KEY_IMA_EXT_1; clean patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1Paul Walmsley3-70/+103
We've run out of bits to describe RISC-V ISA extensions in our initial hwprobe key, RISCV_HWPROBE_KEY_IMA_EXT_0. So, let's add RISCV_HWPROBE_KEY_IMA_EXT_1, along with the framework to set the appropriate hwprobe tuple, and add testing for it. Based on a suggestion from Andrew Jones <andrew.jones@oss.qualcomm.com>, also fix the documentation for RISCV_HWPROBE_KEY_IMA_EXT_0. Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv/ptrace: expose riscv CFI status and state via ptrace and in core filesDeepak Gupta2-0/+125
Expose a new register type NT_RISCV_USER_CFI for risc-v CFI status and state. Intentionally, both landing pad and shadow stack status and state are rolled into the CFI state. Creating two different NT_RISCV_USER_XXX would not be useful and would waste a note type. Enabling, disabling and locking the CFI feature is not allowed via ptrace set interface. However, setting 'elp' state or setting shadow stack pointer are allowed via the ptrace set interface. It is expected that 'gdb' might need to fixup 'elp' state or 'shadow stack' pointer. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-19-b55691eacf4f@rivosinc.com [pjw@kernel.org: updated to apply; cleaned patch description and comments; addressed checkpatch issues] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv/kernel: update __show_regs() to print shadow stack registerDeepak Gupta1-2/+2
Update __show_regs() to print the captured shadow stack pointer. On tasks where shadow stack is disabled, simply print 0. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-18-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned up patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv/signal: save and restore the shadow stack on a signalDeepak Gupta5-0/+158
Save the shadow stack pointer in the sigcontext structure when delivering a signal. Restore the shadow stack pointer from sigcontext on sigreturn. As part of the save operation, the kernel uses the 'ssamoswap' instruction to save a snapshot of the current shadow stack on the shadow stack itself (this can be called a "save token"). During restore on sigreturn, the kernel retrieves the save token from the top of the shadow stack and validates it. This ensures that user mode can't arbitrarily pivot to any shadow stack address without having a token and thus provides a strong security assurance during the window between signal delivery and sigreturn. Use an ABI-compatible way of saving/restoring the shadow stack pointer into the signal stack. This follows the vector extension, where extra registers are placed in a form of extension header + extension body in the stack. The extension header indicates the size of the extra architectural states plus the size of header itself, and a magic identifier for the extension. Then, the extension body contains the new architectural states in the form defined by uapi. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-17-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned patch description, code comments; resolved checkpatch warning] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv/traps: Introduce software check exception and uprobe handlingDeepak Gupta4-0/+60
The Zicfiss and Zicfilp extensions introduce a new exception, the 'software check exception', in the privileged ISA, with cause code = 18. This patch implements support for software check exceptions. Additionally, the patch implements a CFI violation handler which checks the code in the xtval register. If xtval=2, the software check exception happened because of an indirect branch that didn't land on a 4 byte aligned PC or on a 'lpad' instruction, or the label value embedded in 'lpad' didn't match the label value set in the x7 register. If xtval=3, the software check exception happened due to a mismatch between the link register (x1 or x5) and the top of shadow stack (on execution of `sspopchk`). In case of a CFI violation, SIGSEGV is raised with code=SEGV_CPERR. SEGV_CPERR was introduced by the x86 shadow stack patches. To keep uprobes working, handle the uprobe event first before reporting the CFI violation in the software check exception handler. This is because, when the landing pad is activated, if the uprobe point is set at the lpad instruction at the beginning of a function, the system triggers a software check exception instead of an ebreak exception due to the exception priority. This would prevent uprobe from working. Reviewed-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-15-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned up the patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv: Implement indirect branch tracking prctlsDeepak Gupta4-0/+102
This patch adds a RISC-V implementation of the following prctls: PR_SET_INDIR_BR_LP_STATUS, PR_GET_INDIR_BR_LP_STATUS and PR_LOCK_INDIR_BR_LP_STATUS. Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-14-b55691eacf4f@rivosinc.com [pjw@kernel.org: clean up patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv: Implement arch-agnostic shadow stack prctlsDeepak Gupta3-0/+134
Implement an architecture-agnostic prctl() interface for setting and getting shadow stack status. The prctls implemented are PR_GET_SHADOW_STACK_STATUS, PR_SET_SHADOW_STACK_STATUS and PR_LOCK_SHADOW_STACK_STATUS. As part of PR_SET_SHADOW_STACK_STATUS/PR_GET_SHADOW_STACK_STATUS, only PR_SHADOW_STACK_ENABLE is implemented because RISCV allows each mode to write to their own shadow stack using 'sspush' or 'ssamoswap'. PR_LOCK_SHADOW_STACK_STATUS locks the current shadow stack enablement configuration. Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-12-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned up patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv/shstk: If needed allocate a new shadow stack on cloneDeepak Gupta4-0/+162
Userspace specifies CLONE_VM to share address space and spawn new thread. 'clone' allows userspace to specify a new stack for a new thread. However there is no way to specify a new shadow stack base address without changing the API. This patch allocates a new shadow stack whenever CLONE_VM is given. In case of CLONE_VFORK, the parent is suspended until the child finishes; thus the child can use the parent's shadow stack. In case of !CLONE_VM, COW kicks in because entire address space is copied from parent to child. 'clone3' is extensible and can provide mechanisms for specifying the shadow stack as an input parameter. This is not settled yet and is being extensively discussed on the mailing list. Once that's settled, this code should be adapted. Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-11-b55691eacf4f@rivosinc.com [pjw@kernel.org: cleaned up patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29riscv/mm: Implement map_shadow_stack() syscallDeepak Gupta2-0/+141
As discussed extensively in the changelog for the addition of this syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall") the existing mmap() and madvise() syscalls do not map entirely well onto the security requirements for shadow stack memory since they lead to windows where memory is allocated but not yet protected or stacks which are not properly and safely initialised. Instead a new syscall map_shadow_stack() has been defined which allocates and initialises a shadow stack page. This patch implements this syscall for riscv. riscv doesn't require tokens to be setup by kernel because user mode can do that by itself. However to provide compatibility and portability with other architectues, user mode can specify token set flag. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-10-b55691eacf4f@rivosinc.com Link: https://lore.kernel.org/linux-riscv/aXfRPJvoSsOW8AwM@debug.ba.rivosinc.com/ [pjw@kernel.org: added allocate_shadow_stack() fix per Deepak; fixed bug found by sparse] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29Merge tag 'omap-for-v6.20/soc-signed' of ↵Arnd Bergmann2-5/+10
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/arm ARM: omap: soc updates for v6.20 * tag 'omap-for-v6.20/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap: ARM: omap1: drop unused Kconfig symbol ARM: omap2: Fix reference count leaks in omap_control_init() Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29Merge tag 'at91-soc-6.20' of ↵Arnd Bergmann6-72/+8
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm Microchip AT91 SoC updates for v6.20 This update includes: - drop the use of of_platform_default_populate() from the machine specific code, as it is already handled by the DT core * tag 'at91-soc-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: remove unnecessary of_platform_default_populate calls ARM: at91: Move PM init functions to .init_late hook Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29Merge tag 'mtk-defconfig-for-v6.20' of ↵Arnd Bergmann1-0/+1
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig MediaTek defconfig updates This adds a single change, enabling to compile the MediaTek HDMIv2 driver as module. * tag 'mtk-defconfig-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: arm64: defconfig: Enable Mediatek HDMIv2 driver Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29riscv: defconfig: spacemit: k3: enable clock supportYixun Lan1-1/+1
Enable the clock driver support for SpacemiT K3 SoC, configure it as built-in by default, but users should be able to change it as kernel module if needed. Signed-off-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20260128-sitter-crazily-184c1a7606db@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29Merge tag 'ti-k3-config-for-v6.20' of ↵Arnd Bergmann1-0/+3
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/defconfig TI K3 defconfig updates for v6.20 - Enable configurations for Kontron SMARC-sAM67 module support * tag 'ti-k3-config-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: arm64: defconfig: Enable configurations for Kontron SMARC-sAM67 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29Merge tag 'imx-defconfig-6.20' of ↵Arnd Bergmann3-11/+8
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/defconfig i.MX defconfig changes for 6.20: - A couple of changes from Alexander Stein and Andreas Kemnade to enable SND_SOC_FSL_ASOC_CARD and REGULATOR_FP9931 in imx_v6_v7_defconfig - A change from Dmitry Baryshkov to enable DA9052 and MC13XXX in multi_v7_defconfig - A change from Josua Mayer to refresh imx_v4_v5_defconfig by removing stale options and adding missing ones * tag 'imx-defconfig-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx_v4_v5_defconfig: update for v6.19-rc1 ARM: imx_v6_v7_defconfig: enable EPD regulator needed for Kobo Clara 2e ARM: imx_v6_v7_defconfig: Configure CONFIG_SND_SOC_FSL_ASOC_CARD as module ARM: multi_v7_defconfig: enable DA9052 and MC13XXX Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29Merge tag 'qcom-arm64-defconfig-for-6.20' of ↵Arnd Bergmann1-0/+15
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig Qualcomm Arm64 defconfig update for v6.20 Enable drivers needed to boot the Kaanapali and Milos platforms. Enable EC-drivers found on various Qualcomm-based laptops. * tag 'qcom-arm64-defconfig-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: defconfig: Enable EC drivers for Qualcomm-based laptops arm64: defconfig: Enable options for Qualcomm Milos SoC arm64: defconfig: enable clocks, interconnect and pinctrl for Qualcomm Kaanapali Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29Merge tag 'xilinx-defconfig-for-6.20' of ↵Arnd Bergmann1-0/+42
https://github.com/Xilinx/linux-xlnx into soc/defconfig arm64: Xilinx defconfig changes for 6.20 - Enable missing drivers by default * tag 'xilinx-defconfig-for-6.20' of https://github.com/Xilinx/linux-xlnx: arm64: defconfig: Drop duplicate CONFIG_OMAP_USB2 entry arm64: defconfig: Enable missing AMD/Xilinx drivers Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29Merge tag 'apple-soc-defconfig-6.20' of ↵Arnd Bergmann2-0/+28
https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/defconfig Apple SoC defconfig update for 6.20 - Enable most drivers required for Apple Silicon as module inside defconfig - Enable the power-domain driver when ARCH_APPLE and PM is selected since it's critical for booting these systems * tag 'apple-soc-defconfig-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: arm64: defconfig: Enable Apple Silicon drivers arm64: select APPLE_PMGR_PWRSTATE for ARCH_APPLE Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29Merge tag 'renesas-arm-defconfig-for-v6.20-tag1' of ↵Arnd Bergmann2-1/+3
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig Renesas ARM defconfig updates for v6.20 - Enable support for the Renesas RZ/G3E USB3 PHY and RZ/G3S PCIe drivers in the ARM64 defconfig, - Refresh the ARM SH-Mobile defconfig for v6.19-rc1. * tag 'renesas-arm-defconfig-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: shmobile: defconfig: Refresh for v6.19-rc1 arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC arm64: defconfig: Enable RZ/G3E USB3 PHY driver Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29riscv: compat: fix COMPAT_UTS_MACHINE definitionHan Gao1-1/+1
The COMPAT_UTS_MACHINE for riscv was incorrectly defined as "riscv". Change it to "riscv32" to reflect the correct 32-bit compat name. Fixes: 06d0e3723647 ("riscv: compat: Add basic compat data type implementation") Cc: stable@vger.kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn> Reviewed-by: Guo Ren (Alibaba Damo Academy) <guoren@kernel.org> Link: https://patch.msgid.link/20260127190711.2264664-1-gaohan@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-29ARM: defconfig: turn off CONFIG_EXPERTArnd Bergmann1-3/+13
Since multi_v7_defconfig is meant to be the generic defconfig, many users are not going to be experts and it is counterintuitive to have CONFIG_EXPERT enabled. This change has a couple of side-effects: - CONFIG_NAMESPACES is enabled by default. This adds about 0.2% of .text, but is already enabled in many board specific configs, and apparently a requirement for systemd, so this seems like a useful change. - CONFIG_DEBUG_MEMORY_INIT is enabled now, adding a tiny bit of code in the inittext section - CONFIG_RFKILL, CONFIG_MEDIA_SUPPORT_FILTER and various CONFIG_HID driver defaults change, so these have to be listed explicitly to maintain the previous behavior - CONFIG_SERIAL_SH_SCI_NR_UARTS=20 changes to the default value of 18, which I understand to be sufficient for any buard, even if all UARTS are enabled at the same time Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20260112153255.795553-2-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29ARM: defconfig: move entriesArnd Bergmann1-15/+16
Some Kconfig files got rearranged, so change the defconfig file to put everything back in the order used by 'make savedefconfig'. Link: https://lore.kernel.org/r/20260112153255.795553-1-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29net: ethernet: neterion: s2io: remove unused driverEthan Nelson-Moore8-8/+0
The s2io driver supports Exar (formerly Neterion and S2io) PCI-X 10 Gigabit Ethernet cards. Hardware supporting PCI-X has not been manufactured in years. On x86, it was quickly replaced by PCIe. While it stuck around longer on POWER hardware, the last POWER hardware to support it was POWER7, which is not supported by ppc64le Linux distributions. The last supported mainstream ppc64 Linux distribution was RHEL 7; while it is still supported under ELS, ELS is only available for x86 and IBM Z. It is possible to use many PCI-X cards in standard PCI slots (which are still available on new motherboards), but it does not make sense to do so for 10 Gigabit Ethernet because the maximum bandwidth of standard PCI is only 1067 Mbps. It is therefore highly unlikely that this driver is still being used. Remove the driver, and move the former maintainer to the CREDITS file (restoring credit for the vxge driver, which was removed in commit f05643a0f60b ("eth: remove neterion/vxge"). Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com> Link: https://patch.msgid.link/20260126031352.22997-1-enelsonmoore@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-29powerpc/smp: Add check for kcalloc() failure in parse_thread_groups()Guangshuo Li1-0/+2
As kcalloc() may fail, check its return value to avoid a NULL pointer dereference when passing it to of_property_read_u32_array(). Fixes: 790a1662d3a26 ("powerpc/smp: Parse ibm,thread-groups with multiple properties") Cc: stable@vger.kernel.org Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Guangshuo Li <lgs201920130244@gmail.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20250923133235.1862108-1-lgs201920130244@gmail.com
2026-01-29powerpc: kgdb: Remove OUTBUFMAX constantMiquel Sabaté Solà1-1/+0
This constant was introduced in commit 17ce452f7ea3 ("kgdb, powerpc: arch specific powerpc kgdb support"), but it is no longer used anywhere in the source tree. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20250915141808.146695-1-mikisabate@gmail.com
2026-01-29powerpc64/bpf: Additional NVR handling for bpf_throwAbhishek Dubey1-8/+81
The bpf_throw() function never returns, if it has clobbered any callee-saved register, those will remain clobbered. The prologue must take care of saving all callee-saved registers in the frame of exception boundary program. Later these additional non volatile registers R14-R25 along with other NVRs are restored back in the epilogue of exception callback. To achieve above objective, the frame size is determined dynamically to accommodate additional non volatile registers in exception boundary's frame. For non-exception boundary program, the frame size remains optimal. The additional instructions to save & restore r14-r25 registers are emitted only during exception boundary and exception callback program respectively. Signed-off-by: Abhishek Dubey <adubey@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260124075223.6033-7-adubey@linux.ibm.com
2026-01-29powerpc64/bpf: Support exceptionsAbhishek Dubey3-18/+50
The modified prologue/epilogue generation code now enables exception-callback to use the stack frame of the program marked as exception boundary, where callee saved registers are stored. As per ppc64 ABIv2 documentation[1], r14-r31 are callee saved registers. BPF programs on ppc64 already saves r26-r31 registers. Saving the remaining set of callee saved registers(r14-r25) is handled in the next patch. [1] https://ftp.rtems.org/pub/rtems/people/sebh/ABI64BitOpenPOWERv1.1_16July2015_pub.pdf Signed-off-by: Abhishek Dubey <adubey@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260124075223.6033-6-adubey@linux.ibm.com
2026-01-29powerpc64/bpf: Add arch_bpf_stack_walk() for BPF JITAbhishek Dubey1-0/+41
This function is used by bpf_throw() to unwind the stack until frame of exception-boundary during BPF exception handling. This function is necessary to support BPF exceptions on PowerPC. Signed-off-by: Abhishek Dubey <adubey@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260124075223.6033-5-adubey@linux.ibm.com
2026-01-29powerpc64/bpf: Avoid tailcall restore from trampolineAbhishek Dubey1-8/+5
Back propagation of tailcall count is no longer needed for powerpc64 due to use of reference, which updates the tailcall count in the tail_call_info field in the frame of the main program only. Back propagation is still required for 32-bit powerpc. Signed-off-by: Abhishek Dubey <adubey@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260124075223.6033-4-adubey@linux.ibm.com
2026-01-29powerpc64/bpf: Support tailcalls with subprogsAbhishek Dubey3-22/+122
Enable tailcalls support in subprogs by passing tail call count as reference instead of value. The actual tailcall count is always maintained in the tailcall field present in the frame of main function (also called entry function). The tailcall field in the stack frame of subprogs contains reference to the tailcall field in the stack frame of main BPF program. Accordingly, rename tail_call_cnt field in the stack layout to tail_call_info. Signed-off-by: Abhishek Dubey <adubey@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260124075223.6033-3-adubey@linux.ibm.com
2026-01-29powerpc64/bpf: Moving tail_call_cnt to bottom of frameAbhishek Dubey3-14/+24
To support tailcalls in subprogs, tail_call_cnt needs to be on the BPF trampoline stack frame. In a regular BPF program or subprog stack frame, the position of tail_call_cnt is after the NVR save area (BPF_PPC_STACK_SAVE). To avoid complex logic in deducing offset for tail_call_cnt, it has to be kept at the same offset on the trampoline frame as well. But doing that wastes nearly all of BPF_PPC_STACK_SAVE bytes on the BPF trampoline stack frame as the NVR save area is not the same for BPF trampoline and regular BPF programs. Address this by moving tail_call_cnt to the bottom of the frame. This change avoids the need to account for BPF_PPC_STACK_SAVE bytes in the BPF trampoline stack frame when support for tailcalls in BPF subprogs is added later. Also, this change makes offset calculation of tail_call_cnt field simpler all across. Signed-off-by: Abhishek Dubey <adubey@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260124075223.6033-2-adubey@linux.ibm.com
2026-01-29Merge tag 'riscv-dt-for-v6.20' of ↵Arnd Bergmann4-14/+29
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.20 (or v7.0) Anlogic: Minor change to the extension information, to add the "b" extension that's a catch-all for 3 of the extensions already in the dts. Starfive: Append the jh7110 compatible to jh7110s devicetrees, as that will enable OpenSBI etc to run without adding support for this minor variant. The "s" device differs from the non "s" device only in thermal limits and voltage/frequency characteristics. Microchip: Redo the mpfs clock setup yet again, to something approaching correct. The original binding conjured up for the platform was wildly inaccurate, and even with the original improvements, a bigger change to using syscons was required to support several peripherals that also inhabit the memory regions that the clocks lie in. The damage to the dts isn't that bad in the end, and of course the whole thing has been done in a backwards compatible manner, with the code changes being merged a cycle or two ago in the kernel and like a year ago in U-Boot (the only other user that I am aware of). Generic: Additions to extensions.yaml, mainly for things in the "rva23" profile that appear for the first time on the Spacemit K3 SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: anlogic: dr1v90: Add "b" ISA extension dt-bindings: riscv: extensions: Drop unnecessary select schema dt-bindings: riscv: Add Sha and its comprised extensions dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm dt-bindings: riscv: Add B ISA extension description dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board riscv: dts: microchip: convert clock and reset to use syscon riscv: dts: microchip: fix mailbox description Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-29arm64: dts: realtek: Add Kent SoC and EVB device treesYu-Chun Lin11-4/+596
Add Device Tree hierarchy for Realtek Kent SoC family: - kent.dtsi: base SoC layer - rtd<variant>.dtsi: SoC variant layer - rtd<variant>-<board>.dtsi: board layer - rtd<variant>-<board>-<config>.dts: board configuration layer Include RTD1501s Phantom EVB (8GB), RTD1861B Krypton EVB (8GB), and RTD1920s Smallville EVB (4GB). Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20260127071530.25426-3-eleanor15x@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28bpf,x86: Use single ftrace_ops for direct callsJiri Olsa1-0/+1
Using single ftrace_ops for direct calls update instead of allocating ftrace_ops object for each trampoline. With single ftrace_ops object we can use update_ftrace_direct_* api that allows multiple ip sites updates on single ftrace_ops object. Adding HAVE_SINGLE_FTRACE_DIRECT_OPS config option to be enabled on each arch that supports this. At the moment we can enable this only on x86 arch, because arm relies on ftrace_ops object representing just single trampoline image (stored in ftrace_ops::direct_call). Archs that do not support this will continue to use *_ftrace_direct api. Signed-off-by: Jiri Olsa <jolsa@kernel.org> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Acked-by: Andrii Nakryiko <andrii@kernel.org> Reviewed-by: Steven Rostedt (Google) <rostedt@goodmis.org> Link: https://lore.kernel.org/bpf/20251230145010.103439-10-jolsa@kernel.org
2026-01-28Merge tag 'qcom-arm32-for-6.20-2' of ↵Arnd Bergmann3-2/+207
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt More Qualcomm Arm32 DeviceTree updated for v6.20 MSM8226 is switched to generic RPMPD_ indices, to allow dropping the duplicate platform-specific constants. On MSM8960 two additional GSBIs and I2C controllers are introduced. Accelerometer, Magnetometer, NFC and Light/Proximity sensors are then enabled on the Samsung Galaxy Express. * tag 'qcom-arm32-for-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: ARM: dts: qcom: switch to RPMPD_* indices ARM: dts: qcom: msm8960: expressatt: Add Accelerometer ARM: dts: qcom: msm8960: expressatt: Add Magnetometer ARM: dts: qcom: msm8960: expressatt: Add NFC ARM: dts: qcom: msm8960: expressatt: Add Light/Proximity Sensor ARM: dts: qcom: msm8960: Add GSBI2 & GSBI7 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-22 20:11:09 +0300