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2025-07-04Merge tag 'soc-fixes-6.16' of ↵Linus Torvalds7-8/+6
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC fixes from Arnd Bergmann: "A couple of fixes for firmware drivers have come up, addressing kernel side bugs in op-tee and ff-a code, as well as compatibility issues with exynos-acpm and ff-a protocols. The only devicetree fixes are for the Apple platform, addressing issues with conformance to the bindings for the wlan, spi and mipi nodes" * tag 'soc-fixes-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: apple: Move touchbar mipi {address,size}-cells from dtsi to dts arm64: dts: apple: Drop {address,size}-cells from SPI NOR arm64: dts: apple: t8103: Fix PCIe BCM4377 nodename optee: ffa: fix sleep in atomic context firmware: exynos-acpm: fix timeouts on xfers handling arm64: defconfig: update renamed PHY_SNPS_EUSB2 firmware: arm_ffa: Fix the missing entry in struct ffa_indirect_msg_hdr firmware: arm_ffa: Replace mutex with rwlock to avoid sleep in atomic context firmware: arm_ffa: Move memory allocation outside the mutex locking firmware: arm_ffa: Fix memory leak by freeing notifier callback node
2025-07-04Merge tag 'riscv-for-linus-6.16-rc5' of ↵Linus Torvalds2-4/+5
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - kCFI is restricted to clang-17 or newer, as earlier versions have known bugs - sbi_hsm_hart_start is now staticly allocated, to avoid tripping up the SBI HSM page mapping on sparse systems. * tag 'riscv-for-linus-6.16-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: cpu_ops_sbi: Use static array for boot_data riscv: Require clang-17 or newer for kCFI
2025-07-04lib/crypto: sha256: Consolidate into single moduleEric Biggers3-73/+0
Consolidate the CPU-based SHA-256 code into a single module, following what I did with SHA-512: - Each arch now provides a header file lib/crypto/$(SRCARCH)/sha256.h, replacing lib/crypto/$(SRCARCH)/sha256.c. The header defines sha256_blocks() and optionally sha256_mod_init_arch(). It is included by lib/crypto/sha256.c, and thus the code gets built into the single libsha256 module, with proper inlining and dead code elimination. - sha256_blocks_generic() is moved from lib/crypto/sha256-generic.c into lib/crypto/sha256.c. It's now a static function marked with __maybe_unused, so the compiler automatically eliminates it in any cases where it's not used. - Whether arch-optimized SHA-256 is buildable is now controlled centrally by lib/crypto/Kconfig instead of by lib/crypto/$(SRCARCH)/Kconfig. The conditions for enabling it remain the same as before, and it remains enabled by default. - Any additional arch-specific translation units for the optimized SHA-256 code (such as assembly files) are now compiled by lib/crypto/Makefile instead of lib/crypto/$(SRCARCH)/Makefile. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20250630160645.3198-13-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-07-04lib/crypto: sha256: Remove sha256_is_arch_optimized()Eric Biggers1-6/+0
Remove sha256_is_arch_optimized(), since it is no longer used. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20250630160645.3198-12-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-07-04lib/crypto: sha256: Propagate sha256_block_state type to implementationsEric Biggers1-1/+1
The previous commit made the SHA-256 compression function state be strongly typed, but it wasn't propagated all the way down to the implementations of it. Do that now. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20250630160645.3198-8-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-07-04lib/crypto: sha256: Make library API use strongly-typed contextsEric Biggers3-6/+6
Currently the SHA-224 and SHA-256 library functions can be mixed arbitrarily, even in ways that are incorrect, for example using sha224_init() and sha256_final(). This is because they operate on the same structure, sha256_state. Introduce stronger typing, as I did for SHA-384 and SHA-512. Also as I did for SHA-384 and SHA-512, use the names *_ctx instead of *_state. The *_ctx names have the following small benefits: - They're shorter. - They avoid an ambiguity with the compression function state. - They're consistent with the well-known OpenSSL API. - Users usually name the variable 'sctx' anyway, which suggests that *_ctx would be the more natural name for the actual struct. Therefore: update the SHA-224 and SHA-256 APIs, implementation, and calling code accordingly. In the new structs, also strongly-type the compression function state. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20250630160645.3198-7-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-07-04Merge tag 'platform-drivers-x86-v6.16-3' of ↵Linus Torvalds2-14/+1
git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86 Pull x86 platform drivers fixes from Ilpo Järvinen: "Mostly a few lines fixed here and there except amd/isp4 which improves swnodes relationships but that is a new driver not in any stable kernels yet. The think-lmi driver changes also look relatively large but there are just many fixes to it. The i2c/piix4 change is a effectively a revert of the commit 7e173eb82ae9 ("i2c: piix4: Make CONFIG_I2C_PIIX4 dependent on CONFIG_X86") but that required moving the header out from arch/x86 under include/linux/platform_data/ Summary: - amd/isp4: Improve swnode graph (new driver exception) - asus-nb-wmi: Use duo keyboard quirk for Zenbook Duo UX8406CA - dell-lis3lv02d: Add Latitude 5500 accelerometer address - dell-wmi-sysman: Fix WMI data block retrieval and class dev unreg - hp-bioscfg: Fix class device unregistration - i2c: piix4: Re-enable on non-x86 + move FCH header under platform_data/ - intel/hid: Wildcat Lake support - mellanox: - mlxbf-pmc: Fix duplicate event ID - mlxbf-tmfifo: Fix vring_desc.len assignment - mlxreg-lc: Fix bit-not-set logic check - nvsw-sn2201: Fix bus number in error message & spelling errors - portwell-ec: Move watchdog device under correct platform hierarchy - think-lmi: Error handling fixes (sysfs, kset, kobject, class dev unreg) - thinkpad_acpi: Handle HKEY 0x1402 event (2025 Thinkpads) - wmi: Fix WMI event enablement" * tag 'platform-drivers-x86-v6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (22 commits) platform/x86: think-lmi: Fix sysfs group cleanup platform/x86: think-lmi: Fix kobject cleanup platform/x86: think-lmi: Create ksets consecutively platform/mellanox: mlxreg-lc: Fix logic error in power state check i2c: Re-enable piix4 driver on non-x86 Move FCH header to a location accessible by all archs platform/x86/intel/hid: Add Wildcat Lake support platform/x86: dell-wmi-sysman: Fix class device unregistration platform/x86: think-lmi: Fix class device unregistration platform/x86: hp-bioscfg: Fix class device unregistration platform/x86: Update swnode graph for amd isp4 platform/x86: dell-wmi-sysman: Fix WMI data block retrieval in sysfs callbacks platform/x86: wmi: Update documentation of WCxx/WExx ACPI methods platform/x86: wmi: Fix WMI event enablement platform/mellanox: nvsw-sn2201: Fix bus number in adapter error message platform/mellanox: Fix spelling and comment clarity in Mellanox drivers platform/mellanox: mlxbf-pmc: Fix duplicate event ID for CACHE_DATA1 platform/x86: thinkpad_acpi: handle HKEY 0x1402 event platform/x86: asus-nb-wmi: add DMI quirk for ASUS Zenbook Duo UX8406CA platform/x86: dell-lis3lv02d: Add Latitude 5500 ...
2025-07-04arm64/mm: Drop wrong writes into TCR2_EL1Anshuman Khandual1-1/+0
Register X0 contains PIE_E1_ASM and should not be written into REG_TCR2_EL1 which could have an adverse impact otherwise. This has remained undetected till now probably because current value for PIE_E1_ASM (0xcc880e0ac0800000) clears TCR2_EL1 which again gets set subsequently with 'tcr2' after testing for FEAT_TCR2. Drop this unwarranted 'msr' which is a stray change from an earlier commit. This line got re-introduced when rebasing on top of the commit 926b66e2ebc8 ("arm64: setup: name 'tcr2' register"). Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Fixes: 7052e808c446 ("arm64/sysreg: Get rid of the TCR2_EL1x SysregFields") Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20250704063812.298914-1-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-07-04arm64: poe: Handle spurious Overlay faultsKevin Brodsky2-9/+26
We do not currently issue an ISB after updating POR_EL0 when context-switching it, for instance. The rationale is that if the old value of POR_EL0 is more restrictive and causes a fault during uaccess, the access will be retried [1]. In other words, we are trading an ISB on every context-switching for the (unlikely) possibility of a spurious fault. We may also miss faults if the new value of POR_EL0 is more restrictive, but that's considered acceptable. However, as things stand, a spurious Overlay fault results in uaccess failing right away since it causes fault_from_pkey() to return true. If an Overlay fault is reported, we therefore need to double check POR_EL0 against vma_pkey(vma) - this is what arch_vma_access_permitted() already does. As it turns out, we already perform that explicit check if no Overlay fault is reported, and we need to keep that check (see comment added in fault_from_pkey()). Net result: the Overlay ISS2 bit isn't of much help to decide whether a pkey fault occurred. Remove the check for the Overlay bit from fault_from_pkey() and add a comment to try and explain the situation. While at it, also add a comment to permission_overlay_switch() in case anyone gets surprised by the lack of ISB. [1] https://lore.kernel.org/linux-arm-kernel/ZtYNGBrcE-j35fpw@arm.com/ Fixes: 160a8e13de6c ("arm64: context switch POR_EL0 register") Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com> Link: https://lore.kernel.org/r/20250619160042.2499290-2-kevin.brodsky@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-07-04arm64: Filter out SME hwcaps when FEAT_SME isn't implementedMark Brown1-25/+32
We have a number of hwcaps for various SME subfeatures enumerated via ID_AA64SMFR0_EL1. Currently we advertise these without cross checking against the main SME feature, advertised in ID_AA64PFR1_EL1.SME which means that if the two are out of sync userspace can see a confusing situation where SME subfeatures are advertised without the base SME hwcap. This can be readily triggered by using the arm64.nosme override which only masks out ID_AA64PFR1_EL1.SME, and there have also been reports of VMMs which do the same thing. Fix this as we did previously for SVE in 064737920bdb ("arm64: Filter out SVE hwcaps when FEAT_SVE isn't implemented") by filtering out the SME subfeature hwcaps when FEAT_SME is not present. Fixes: 5e64b862c482 ("arm64/sme: Basic enumeration support") Reported-by: Yury Khrustalev <yury.khrustalev@arm.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250620-arm64-sme-filter-hwcaps-v1-1-02b9d3c2d8ef@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2025-07-04arm64: move smp_send_stop() cpu mask off stackArnd Bergmann1-1/+1
For really large values of CONFIG_NR_CPUS, a CPU mask value should not be put on the stack: arch/arm64/kernel/smp.c:1188:1: error: the frame size of 8544 bytes is larger than 1536 bytes [-Werror=frame-larger-than=] This could be achieved using alloc_cpumask_var(), which makes it depend on CONFIG_CPUMASK_OFFSTACK, but as this function is already serialized and can only run on one CPU, making the variable 'static' is easier. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20250620111045.3364827-1-arnd@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2025-07-04arm64/gcs: Don't try to access GCS registers if arm64.nogcs is enabledMark Brown1-12/+7
During EL2 setup if GCS is advertised in the ID registers we will reset the GCS control registers GCSCR_EL1 and GCSCRE0_EL1 to known values in order to ensure it is disabled. This is done without taking into account overrides supplied on the command line, meaning that if the user has configured arm64.nogcs we will still access these GCS specific registers. If this was done because EL3 does not enable GCS this results in traps to EL3 and a failed boot which is not what users would expect from having set that parameter. Move the writes to these registers to finalise_el2_state where we can pay attention to the command line overrides. For simplicity we leave the updates to the traps in HCRX_EL2 and the FGT registers in place since these should only be relevant for KVM guests and KVM will manage them itself for guests. This follows the existing practice for other similar traps for overridable features such as those for TPIDR2_EL0 and SMPRI_EL1. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20250619-arm64-fix-nogcs-v1-1-febf2973672e@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2025-07-04arm64: dts: amlogic: Enable the npu node for Alta and VIM3Tomeu Vizoso2-0/+8
We now have support in Mesa and everything is ready in distros such as Debian. Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Link: https://lore.kernel.org/r/20250522092940.3293889-1-tomeu@tomeuvizoso.net Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-07-04dts: arm64: amlogic: add S6 pinctrl nodeXianwei Zhao1-0/+97
Add pinctrl device to support Amlogic S6. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20250527-s6-s7-pinctrl-v3-6-44f6a0451519@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-07-04dts: arm64: amlogic: add S7D pinctrl nodeXianwei Zhao1-0/+90
Add pinctrl device to support Amlogic S7D. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20250527-s6-s7-pinctrl-v3-5-44f6a0451519@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-07-04dts: arm64: amlogic: add S7 pinctrl nodeXianwei Zhao1-0/+81
Add pinctrl device to support Amlogic S7. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20250527-s6-s7-pinctrl-v3-4-44f6a0451519@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-07-04arm64: dts: amlogic: Add Ugoos AM3J. Neuschäfer3-1/+93
The Ugoos AM3 is a small set-top box based on the Amlogic S912 SoC, with a board design that is very close to the Q20x development boards. The MMC max-frequency properties are copied from the downstream device tree. https://ugoos.com/ugoos-am3-16g The following functionality has been tested and is known to work: - debug serial port - "update" button inside the case - USB host mode, on all three ports - HDMI video/audio output - eMMC, MicroSD, and SDIO WLAN - S/PDIF audio output - Ethernet - Infrared remote control input The following functionality doesn't seem to work: - USB role switching and device mode on the "OTG" port - case LED Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: J. Neuschäfer <j.ne@posteo.net> Link: https://lore.kernel.org/r/20250613-ugoos-am3-v3-2-f8a43e6bbfdb@posteo.net Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-07-04arm64: dts: amlogic: Align wifi node name with bindingsKrzysztof Kozlowski1-1/+1
Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: meson-gxm-rbox-pro.dtb: brcmf@1: $nodename:0: 'brcmf@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250424084721.105113-1-krzysztof.kozlowski@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-07-04arm64: Unconditionally select CONFIG_JUMP_LABELMarc Zyngier2-2/+2
Aneesh reports that his kernel fails to boot in nVHE mode with KVM's protected mode enabled. Further investigation by Mostafa reveals that this fails because CONFIG_JUMP_LABEL=n and that we have static keys shared between EL1 and EL2. While this can be worked around, it is obvious that we have long relied on having CONFIG_JUMP_LABEL enabled at all times, as all supported compilers now have 'asm goto' (which is the basic block for jump labels). Let's simplify our lives once and for all by mandating jump labels. It's not like anyone else is testing anything without them, and we already rely on them for other things (kfence, xfs, preempt). Link: https://lore.kernel.org/r/yq5ah60pkq03.fsf@kernel.org Reported-by: Aneesh Kumar K.V <aneesh.kumar@kernel.org> Reported-by: Mostafa Saleh <smostafa@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Catalin marinas <catalin.marinas@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ardb@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20250613141936.2219895-1-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2025-07-04arm64: efi: Fix KASAN false positive for EFI runtime stackBreno Leitao1-3/+8
KASAN reports invalid accesses during arch_stack_walk() for EFI runtime services due to vmalloc tagging[1]. The EFI runtime stack must be allocated with KASAN tags reset to avoid false positives. This patch uses arch_alloc_vmap_stack() instead of __vmalloc_node() for EFI stack allocation, which internally calls kasan_reset_tag() The changes ensure EFI runtime stacks are properly sanitized for KASAN while maintaining functional consistency. Link: https://lore.kernel.org/all/aFVVEgD0236LdrL6@gmail.com/ [1] Suggested-by: Andrey Konovalov <andreyknvl@gmail.com> Suggested-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Breno Leitao <leitao@debian.org> Link: https://lore.kernel.org/r/20250704-arm_kasan-v2-1-32ebb4fd7607@debian.org Signed-off-by: Will Deacon <will@kernel.org>
2025-07-04arm64/watchdog_hld: Add a cpufreq notifier for update watchdog threshYicong Yang1-0/+58
arm64 depends on the cpufreq driver to gain the maximum cpu frequency to convert the watchdog_thresh to perf event period. cpufreq drivers like cppc_cpufreq will be initialized lately after the initializing of the hard lockup detector so just use a safe cpufreq which will be inaccurency. Use a cpufreq notifier to adjust the event's period to a more accurate one. Reviewed-by: Jie Zhan <zhanjie9@hisilicon.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Link: https://lore.kernel.org/r/20250701110214.27242-3-yangyicong@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
2025-07-04um: virtio_pcidev: Rename UM_PCI_STAT_WAITINGTiwei Bie1-4/+4
Rename it to VIRTIO_PCIDEV_STAT_WAITING to make the code slightly more consistent. It was missed when refactoring virtio_pcidev into a separate module. Signed-off-by: Tiwei Bie <tiwei.btw@antgroup.com> Link: https://patch.msgid.link/20250606124428.148164-3-tiwei.btw@antgroup.com Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2025-07-04arm64: defconfig: Enable STM32 Octo Memory Manager and OcstoSPI driverPatrice Chotard1-0/+2
Enable STM32 OctoSPI driver. Enable STM32 Octo Memory Manager (OMM) driver which is needed for OSPI usage on STM32MP257F-EV1 board. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250630-upstream_omm_ospi_defconfig-v11-1-6e934fabe698@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: add stm32mp157f-dk2 board supportAmelie Delaunay3-1/+377
STM32MP157F-DK2 board embeds a STM32MP157F SoC. This SoC contains the same level of feature than a STM32MP157C SOC but A7 clock frequency can reach 800MHz, hence the inclusion of the newly introduced stm32mp15xf.dtsi. As for other latest STM32 MPU families, STM32MP157F-DK2 relies on OP-TEE SCMI services for SoC clock and reset controllers resources, and for PMIC, now under OP-TEE control. That's why stm32mp157f-dk2-scmi.dtsi is introduced, to move all clocks, resets and regulators to SCMI-based ones. To "disable" SCMI, just need to comment stm32mp157f-dk2-scmi.dtsi inclusion and to replace &scmi_v3v3 with &v3v3, then to disable arm_wdt and to enable i2c4 and its subnodes for PMIC support by Linux. Reconfigure usbotg for dual role with type-C support if needed. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-7-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: optee async notif interrupt for MP15 scmi variantsEtienne Carriere1-0/+2
Define the interrupt used by OP-TEE async notif on stm32mp15 scmi based platforms. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-5-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: use internal regulators bindings for MP15 scmi variantsAmelie Delaunay1-3/+5
Use the SCMI voltage domain bindings for internal regulators on stm32mp15. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-4-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkxAmelie Delaunay1-1/+1
Adopt generic node name 'typec' for stusb1600, which is the USB Type-C controller on stm32mp157x Discovery Kits. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-2-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCsAlexandre Torgue1-0/+17
This commit creates new file to manage security features and supported OPP on STM32MP15xF SOCs. On STM32MP15xY, "Y" gives information: -Y = A means no cryp IP and no secure boot + A7-CPU@650MHz. -Y = C means cryp IP + optee + secure boot + A7-CPU@650MHz. -Y = D means no cryp IP and no secure boot + A7-CPU@800MHz. -Y = F means cryp IP + optee + secure boot + A7-CPU@800MHz. It fullfills the initial STM32MP15x SoC diversity introduced by commit 0eda69b6c5f9 ("ARM: dts: stm32: Manage security diversity for STM32M15x SOCs"). Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-1-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkxOlivier Moysan1-0/+1
The commit 5725bce709db ("ASoC: simple-card-utils: Unify clock direction by clk_direction") corrupts the audio on STM32MP15 DK sound cards. The parent clock is not correctly set, because set_sai_ck_rate() is not executed in stm32_sai_set_sysclk() callback. This occurs because set_sysclk() is called with the wrong direction, SND_SOC_CLOCK_IN instead of SND_SOC_CLOCK_OUT. Add system-clock-direction-out property in SAI2A endpoint node of STM32MP15XX-DKX device tree, to specify the MCLK clock direction. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Link: https://lore.kernel.org/r/20250521150418.488152-1-olivier.moysan@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: defconfig: enable STM32 timers driversFabrice Gasnier1-0/+4
Enable the STM32 timer drivers: MFD, counter, PWM and trigger as module. These drivers can be used on STM32MP25. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-6-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer nodes on stm32mp257f-ev1Fabrice Gasnier1-0/+58
Configure timer nodes on stm32mp257f-ev1: - Timer3 CH2 is available on mikroBUS connector for PWM - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector. Timers are kept disabled by default, so the pins can be used for any other purpose (and the timers can be assigned to any of the processors). Arbitrary choice is to use all these timers as PWM (or counter on internal clock signal), except for timer10 that is configured with CH1 as an input (for capture). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-9-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer pins for stm32mp257f-ev1Fabrice Gasnier1-0/+61
Add timer pins available on stm32mp257f-ev1, configured for PWM: - timer3 CH2 is available on mikroBUS connector - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector Arbitrary define all these pins to be used as PWM (output) channels, except for timer10 CH1, to be used as counter input. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-8-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer nodes on stm32mp251Fabrice Gasnier1-0/+524
Add timers support on STM32MP25 SoC. Use dedicated compatible to handle new features and instances introduced with this SoC. STM32MP25 SoC has various timer flavours, each group has its own specific feature list: - Advanced-control timers (TIM1/TIM8/TIM20) - General-purpose timers (TIM2/TIM3/TIM4/TIM5) - Basic timers (TIM6/TIM7) - General-purpose timers (TIM10/TIM11/TIM12/TIM13/TIM14) - General purpose timers (TIM15/TIM16/TIM17) Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-7-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: Switch to new sys-off handler APIAndrew Davis5-5/+5
Kernel now supports chained power-off handlers. Use register_platform_power_off() that registers a platform level power-off handler. Legacy pm_power_off() will be removed once all drivers and archs are converted to the new sys-off API. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250624184245.343657-1-afd@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-04ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addressesUwe Kleine-König2-0/+4
The efuse device tree description already has the two labels pointing to the efuse nodes that specify the mac-addresses to be used. Wire them up to the ethernet nodes. This is enough to make barebox pick the right mac-addresses and pass them to Linux. Suggested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20250328171406.3307778-2-u.kleine-koenig@baylibre.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04Merge tag 'arm-soc/for-6.17/defconfig-arm64' of ↵Arnd Bergmann1-0/+4
https://github.com/Broadcom/stblinux into soc/defconfig This pull request contains ARM64 defconfig updates for 6.17, please pull the following: - Andrea updates the defconfig to enable the RP1 misc, clock and gpio drivers as as well as turn on CONFIG_OF_OVERLAY which is necessary to apply the RP1 overlay file * tag 'arm-soc/for-6.17/defconfig-arm64' of https://github.com/Broadcom/stblinux: arm64: defconfig: Enable OF_OVERLAY option arm64: defconfig: Enable RP1 misc/clock/gpio drivers Link: https://lore.kernel.org/r/20250630190216.1518354-1-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-04Merge tag 'renesas-arm-defconfig-for-v6.17-tag1' of ↵Arnd Bergmann2-0/+2
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig Renesas ARM defconfig updates for v6.17 - Enable modular support for Renesas RZ/V2H USB2PHY Port Reset Control in the ARM64 defconfig, - Refresh shmobile_defconfig for v6.16-rc2. * tag 'renesas-arm-defconfig-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: shmobile: defconfig: Refresh for v6.16-rc2 arm64: defconfig: Enable RZ/V2H(P) USB2 PHY controller reset driver Link: https://lore.kernel.org/r/cover.1751026659.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-04Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netPaolo Abeni63-166/+281
Cross-merge networking fixes after downstream PR (net-6.16-rc5). No conflicts. No adjacent changes. Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-07-04arm64: dts: ti: k3-am62p-verdin: add SD_1 CD pull-upFrancesco Dolcini1-1/+1
Add internal pull-up to the SD_1 card detect signal, without this the CD signal is floating and spurious detects events can happen. Fixes: 87f95ea316ac ("arm64: dts: ti: Add Toradex Verdin AM62P") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250701081643.71406-1-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-04ARM: dts: aspeed: yosemite4: add gpio name for uart mux selMarshall Zhan1-0/+40
Add gpio line name to support multiplexed console Signed-off-by: Marshall Zhan <marshall_zhan@wiwynn.com> Link: https://patch.msgid.link/20250630073138.3315947-1-marshall_zhan@wiwynn.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: santabarbara: Add Meta Santabarbara BMCFred Chen2-0/+983
Add linux device tree entry related to the Meta (Facebook) compute node system using an AST2600 BMC. This node is named "Santabarbara". It is a compute node with accelerator module. The system monitors voltage and temperature for the CPU, switch, and NIC components on the motherboard and switch board. Signed-off-by: Fred Chen <fredchen.openbmc@gmail.com> Link: https://patch.msgid.link/20250625073847.4054971-3-fredchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: bletchley: enable USB PD negotiationCosmo Chou1-24/+42
- Enable USB Power Delivery with revision 2.0 for all sleds - Configure dual power/data roles with sink preference Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Link: https://patch.msgid.link/20250622034247.3985727-1-chou.cosmo@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: lanyang: Fix 'lable' typo in LED nodesAnkit Chauhan1-2/+2
Fix an obvious spelling error in the DTS file for the Lanyang BMC ("lable" -> "label"). This was reported by bugzilla a few years ago but never got fixed. Reported-by: Jens Schleusener <Jens.Schleusener@fossies.org> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=205891 Signed-off-by: Ankit Chauhan <ankitchauhan2065@gmail.com> Link: https://patch.msgid.link/20250612075057.80433-1-ankitchauhan2065@gmail.com [arj: Replace U+2192 with '->'] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add mmc healthPeter Yin1-0/+19
Add a GPIO expander node at address 0x13 on i2c11 bus to monitor MMC health status via a dedicated GPIO line. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-6-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: Harma: revise gpio bride pin for batteryPeter Yin1-2/+2
Update the GPIO bridge pin configuration for the battery circuit on the Harma platform to reflect the correct hardware design. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-5-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add ADC128D818 for voltage monitoringPeter Yin1-0/+13
Add the ADC128D818 device to I2C bus 29 to support voltage monitoring on the Harma platform. This enables accurate measurement of system voltages through the onboard ADC. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-4-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add fan board I/O expanderPeter Yin1-0/+38
Add GPIO I/O expander node for the fan board to detect and monitor fan board status. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-3-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add E1.S power monitorPeter Yin1-0/+11
Add the E1.S power monitor device node to the Harma device tree to enable power monitoring functionality for E1.S drives. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-2-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC managementPotin Lai1-0/+12
Add the `mctp-controller` property and MCTP nodes to enable support for frontend NIC management via PLDM over MCTP. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250611-catalina-mctp-i2c-10-15-v1-1-2a882e461ed9@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04bpf: Add function to find program from stack traceKumar Kartikeya Dwivedi1-1/+0
In preparation of figuring out the closest program that led to the current point in the kernel, implement a function that scans through the stack trace and finds out the closest BPF program when walking down the stack trace. Special care needs to be taken to skip over kernel and BPF subprog frames. We basically scan until we find a BPF main prog frame. The assumption is that if a program calls into us transitively, we'll hit it along the way. If not, we end up returning NULL. Contextually the function will be used in places where we know the program may have called into us. Due to reliance on arch_bpf_stack_walk(), this function only works on x86 with CONFIG_UNWINDER_ORC, arm64, and s390. Remove the warning from arch_bpf_stack_walk as well since we call it outside bpf_throw() context. Acked-by: Eduard Zingerman <eddyz87@gmail.com> Reviewed-by: Emil Tsalapatis <emil@etsalapatis.com> Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com> Link: https://lore.kernel.org/r/20250703204818.925464-6-memxor@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-15 15:25:22 +0300