summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2022-11-22x86/fpu: Use _Alignof to avoid undefined behavior in TYPE_ALIGNYingChi Long1-5/+2
WG14 N2350 specifies that it is an undefined behavior to have type definitions within offsetof", see https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2350.htm This specification is also part of C23. Therefore, replace the TYPE_ALIGN macro with the _Alignof builtin to avoid undefined behavior. (_Alignof itself is C11 and the kernel is built with -gnu11). ISO C11 _Alignof is subtly different from the GNU C extension __alignof__. Latter is the preferred alignment and _Alignof the minimal alignment. For long long on x86 these are 8 and 4 respectively. The macro TYPE_ALIGN's behavior matches _Alignof rather than __alignof__. [ bp: Massage commit message. ] Signed-off-by: YingChi Long <me@inclyc.cn> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Link: https://lore.kernel.org/r/20220925153151.2467884-1-me@inclyc.cn
2022-11-22x86/alternative: Consistently patch SMP locks in vmlinux and modulesJulian Pidancet1-6/+5
alternatives_smp_module_add() restricts patching of SMP lock prefixes to the text address range passed as an argument. For vmlinux, patching all the instructions located between the _text and _etext symbols is allowed. That includes the .text section but also other sections such as .text.hot and .text.unlikely. As per the comment inside the 'struct smp_alt_module' definition, the original purpose of this restriction is to avoid patching the init code because in the case when one boots with a single CPU, the LOCK prefixes to the locking primitives are removed. Later on, when other CPUs are onlined, those LOCK prefixes get added back in but by that time the .init code is very likely removed so patching that would be a bad idea. For modules, the current code only allows patching instructions located inside the .text segment, excluding other sections such as .text.hot or .text.unlikely, which may need patching. Make patching of the kernel core and modules more consistent by allowing all text sections of modules except .init.text to be patched in module_finalize(). For that, use mod->core_layout.base/mod->core_layout.text_size as the address range allowed to be patched, which include all the code sections except the init code. [ bp: Massage and expand commit message. ] Signed-off-by: Julian Pidancet <julian.pidancet@oracle.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221027204906.511277-1-julian.pidancet@oracle.com
2022-11-22ARM: dts: Unify pwm-omap-dmtimer node namesTony Lindgren6-7/+8
There is no reg property for pwm-omap-dmtimer. Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-11-22MIPS: vpe-cmp: fix possible memory leak while module exitingYang Yingliang1-2/+2
dev_set_name() allocates memory for name, it need be freed when module exiting, call put_device() to give up reference, so that it can be freed in kobject_cleanup() when the refcount hit to 0. The vpe_device is static, so remove kfree() from vpe_device_release(). Fixes: 17a1d523aa58 ("MIPS: APRP: Add VPE loader support for CMP platforms.") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-11-22MIPS: vpe-mt: fix possible memory leak while module exitingYang Yingliang1-2/+2
Afer commit 1fa5ae857bb1 ("driver core: get rid of struct device's bus_id string array"), the name of device is allocated dynamically, it need be freed when module exiting, call put_device() to give up reference, so that it can be freed in kobject_cleanup() when the refcount hit to 0. The vpe_device is static, so remove kfree() from vpe_device_release(). Fixes: 1fa5ae857bb1 ("driver core: get rid of struct device's bus_id string array") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-11-22ARM: OMAP2+: Drop legacy hwmod data for omap3 otgTony Lindgren1-99/+0
With complete devicetree data available to probe with ti-sysc interconnect target module driver, we can now drop the related SoC data. Cc: H. Nikolaus Schaller <hns@goldelico.com> Tested-by: Sicelo A. Mhlongo <absicsz@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-11-22ARM: dts: Update omap3 musb to probe with ti-syscTony Lindgren4-17/+69
We can drop the legacy booting for the related musb driver if we update the omap3 SoCs variants to boot using ti-sysc interconnect target module. devicetree@vger.kernel.org Cc: H. Nikolaus Schaller <hns@goldelico.com> Tested-by: Sicelo A. Mhlongo <absicsz@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-11-22x86/ioremap: Fix page aligned size calculation in __ioremap_caller()Michael Kelley1-1/+7
Current code re-calculates the size after aligning the starting and ending physical addresses on a page boundary. But the re-calculation also embeds the masking of high order bits that exceed the size of the physical address space (via PHYSICAL_PAGE_MASK). If the masking removes any high order bits, the size calculation results in a huge value that is likely to immediately fail. Fix this by re-calculating the page-aligned size first. Then mask any high order bits using PHYSICAL_PAGE_MASK. Fixes: ffa71f33a820 ("x86, ioremap: Fix incorrect physical address handling in PAE mode") Signed-off-by: Michael Kelley <mikelley@microsoft.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: <stable@kernel.org> Link: https://lore.kernel.org/r/1668624097-14884-2-git-send-email-mikelley@microsoft.com
2022-11-22ARM: dts: am335x: Fix TDA998x ports addressingGeert Uytterhoeven2-2/+12
Fix addressing in the NXP TDA998x HDMI transmitters' subnodes: - Add missing #{address,size}-cells properties to ports capsule, - Add missing reg properties to port child nodes, - Drop bogus unit addresses from endpoint grandchildren nodes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Message-Id: <e9ac64d29bc18b3b394fd9a2abbfeafacc624f98.1669047037.git.geert+renesas@glider.be> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-11-22ARM: dts: nuvoton: wpcm450: Add missing aliases for serial0/serial1Jonathan Neuschäfer1-0/+5
Without these, /chosen/stdout-path = "serial0:115200n8" does not work. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221008130822.1227104-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-22ARM: dts: wpcm450: Enable watchdog by defaultJonathan Neuschäfer2-5/+0
The watchdog timer is always usable, regardless of board design, so there is no point in marking the watchdog device as disabled-by-default in nuvoton-wpcm450.dtsi. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220609214830.127003-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-22ARM: dts: wpcm450: Add clock controller nodeJonathan Neuschäfer1-0/+17
This declares the clock controller and the necessary 48 Mhz reference clock in the WPCM450 device. Switching devices over to the clock controller is intentionally done in a separate patch to give time for the clock controller driver to land. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221104161850.2889894-5-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-22ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add SPI flashJonathan Neuschäfer1-0/+9
Add the BMC firmware flash to the devicetree, so that it can be accessed from Linux. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-7-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-22ARM: dts: wpcm450: Add FIU SPI controller nodeJonathan Neuschäfer1-0/+16
Add the SPI controller (FIU, Flash Interface Unit) to the WPCM450 devicetree, according to the newly defined binding, as well as the SHM (shared memory interface) syscon. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-6-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-22arm64: dts: ti: Add k3-j721e-beagleboneai64Robert Nelson2-0/+1056
BeagleBoard.org BeagleBone AI-64 is an open source hardware single board computer based on the Texas Instruments TDA4VM SoC featuring dual-core 2.0GHz Arm Cortex-A72 processor, C7x+MMA and 2 C66x floating-point VLIW DSPs, 3x dual Arm Cortex-R5 co-processors, 2x 6-core Programmable Real-Time Unit and Industrial Communication SubSystem, PowerVR Rogue 8XE GE8430 3D GPU. The board features 4GB DDR4, USB3.0 Type-C, 2x USB SS Type-A, miniDisplayPort, 2x 4-lane CSI, DSI, 16GB eMMC flash, 1G Ethernet, M.2 E-key for WiFi/BT, and BeagleBone expansion headers. This board family can be indentified by the BBONEAI-64-B0 in the at24 eeprom: [aa 55 33 ee 01 37 00 10 2e 00 42 42 4f 4e 45 41 |.U3..7....BBONEA|] [49 2d 36 34 2d 42 30 2d 00 00 42 30 30 30 37 38 |I-64-B0-..B00078|] https://beagleboard.org/ai-64 https://git.beagleboard.org/beagleboard/beaglebone-ai-64 Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Andrew Davis <afd@ti.com> CC: Nishanth Menon <nm@ti.com> CC: Vignesh Raghavendra <vigneshr@ti.com> CC: Tero Kristo <kristo@kernel.org> CC: Jason Kridner <jkridner@beagleboard.org> CC: Drew Fustini <drew@beagleboard.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221118163139.3592054-2-robertcnelson@gmail.com
2022-11-21arm64: dts: mt7986: add spi related device nodesSam Shih3-0/+98
This patch adds spi support for MT7986. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21arm64: dts: mt7986: move wed_pcie nodeFrank Wunderlich1-6/+6
Move the wed_pcie node to have node aligned by address. Fixes: 00b9903996b3 ("arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221118190126.100895-2-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21mips: dts: brcm: bcm7435: add "interrupt-names" for NAND controllerRafał Miłecki1-0/+1
Second interrupt can be DMA or EDU one. Specify it explicitly using interrupt-names property. This matches documented binding. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-11-21mips: dts: bcm63268: add TWD block timerRafał Miłecki1-0/+5
BCM63268 TWD contains block with 3 timers. Add binding for it. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-11-21MIPS: Use "grep -E" instead of "egrep"Tiezhu Yang2-2/+2
The latest version of grep claims the egrep is now obsolete so the build now contains warnings that look like: egrep: warning: egrep is obsolescent; using grep -E fix this up by moving the related file to use "grep -E" instead. Here are the steps to install the latest grep: wget http://ftp.gnu.org/gnu/grep/grep-3.8.tar.gz tar xf grep-3.8.tar.gz cd grep-3.8 && ./configure && make sudo make install export PATH=/usr/local/bin:$PATH Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-11-21MIPS: DTS: CI20: fix reset line polarity of the ethernet controllerDmitry Torokhov1-1/+1
The reset line is called PWRST#, annotated as "active low" in the binding documentation, and is driven low and then high by the driver to reset the chip. However in device tree for CI20 board it was incorrectly marked as "active high". Fix it. Because (as far as I know) the ci20.dts is always built in the kernel I elected not to also add a quirk to gpiolib to force the polarity there. Fixes: db49ca38579d ("net: davicom: dm9000: switch to using gpiod API") Reported-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-11-21Merge tag 'am335x-pcm-953-regulators' of ↵Arnd Bergmann1-15/+13
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes Regulator changes for am335x-pcm-953 This is for deferred probe issue on am335x-pcm-953 sdhci-omap regulator. * tag 'am335x-pcm-953-regulators' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x-pcm-953: Define fixed regulators in root node Link: https://lore.kernel.org/r/pull-1669036672-530717@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'renesas-arm-dt-for-v6.2-tag2' of ↵Arnd Bergmann10-37/+522
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas ARM DT updates for v6.2 (take two) - Timer (TMU and CMT) and quad Cortex-A76 CPU topology support for the R-Car V4H SoC, - Watchdog, L2 cache, and system controller support for the RZ/V2M SoC on the RZ/V2M Evaluation Kit 2.0, - Ethernet Switch and SERDES supports for the R-Car S4-8 SoC and the Spider development board, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits) arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDES arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes arm64: dts: renesas: r9a09g011: Add system controller node arm64: dts: renesas: r8a779g0: Add CA76 operating points arm64: dts: renesas: r8a779g0: Add CPU core clocks arm64: dts: renesas: r8a779g0: Add CPUIdle support arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores arm64: dts: renesas: r8a779g0: Add L3 cache controller arm64: dts: renesas: r9a09g011: Add L2 Cache node arm64: dts: renesas: rzv2mevk2: Enable watchdog arm64: dts: renesas: r9a09g011: Add watchdog node arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0 arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes arm64: dts: renesas: r9a09g011: Fix I2C SoC specific strings arm64: dts: renesas: rzg2l: Add missing cache-level properties arm64: dts: renesas: r8a779g0: Add CMT node arm64: dts: renesas: r9a09g011: Fix unit address format error arm64: dts: renesas: white-hawk-cpu: Sort RWDT entry correctly arm64: dts: renesas: r8a779g0: Add TMU nodes arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock ... Link: https://lore.kernel.org/r/cover.1668788921.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'renesas-riscv-dt-for-v6.2-tag1' of ↵Arnd Bergmann6-0/+200
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas RISC-V DT updates for v6.2 - Add initial support for the Renesas RZ/Five SoC and the Renesas RZ/Five SMARC EVK development board. * tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU MAINTAINERS: Add entry for Renesas RISC-V riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Link: https://lore.kernel.org/r/cover.1668788930.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'stm32-dt-for-v6.2-1' of ↵Arnd Bergmann19-24/+537
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.2, round 1 Highlights: ---------- - MPU: - ST boards: - Add MCP23017 IO expander support on stm32mp135f-dk board. - Add stm32g0 support for USB typeC on stm32mp135f-dk - Add USB (EHCI / OTG) on stm32mp135f-dk - Add ADC support on stm32mp135f-dk - Add USB2514B onboard hub on stm32mp157c-ev1 - DH: - Fix severals Yaml DT validation issues * tag 'stm32-dt-for-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (28 commits) ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench board ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13 ARM: dts: stm32: enable USB OTG in dual role mode on stm32mp135f-dk ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13 ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk ARM: dts: stm32: add fixed regulators to support usb on stm32mp135f-dk ARM: dts: stm32: add USB OTG HS support on stm32mp131 ARM: dts: stm32: add UBSH EHCI and OHCI support on stm32mp131 ARM: dts: stm32: add USBPHYC and dual USB HS PHY support on stm32mp131 ARM: dts: stm32: add PWR fixed regulators on stm32mp131 ARM: dts: stm32: Fix AV96 WLAN regulator gpio property ARM: dts: stm32: add adc support on stm32mp135f-dk ARM: dts: stm32: add dummy vdd_adc regulator on stm32mp135f-dk ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk ARM: dts: stm32: add adc support to stm32mp13 ARM: dts: stm32: Drop MMCI interrupt-names ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1 ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1 ... Link: https://lore.kernel.org/r/3235e5be-d89f-f76c-5e25-5d1210feb857@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi ↵Arnd Bergmann5-0/+28
into soc/dt ARM64: DT: HiSilicon ARM64 DT updates for 6.2 - Add missing cache-level properties * tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi: arm64: dts: Update cache properties for hisilicon Link: https://lore.kernel.org/r/63744D38.9010700@hisilicon.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'imx-dt64-6.2' of ↵Arnd Bergmann75-148/+2309
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX arm64 device tree update for 6.2: - New device trees for i.MX8MM based Cloos PHG and WB15 SoM/EVK. - A set of tqma8mpql/mba8mpxl changes, adding USB Host, PCIe, PWM fan support. - Rename DTB overlay source files from .dts to .dtso. - A series from Frank Li to add USB, ADC, FlexSPI, LPSPI support for i.MX8DXL. - A couple of librem5-devkit changes, switching LED to use PWM and using function and color properties for LED. - Enable wakeup-source for USB PHY for i.MX8MM/N EVK. - A set of random changes from Marcel Ziswiler to improve i.MX8M based Verdin device trees. - A series from Marek Vasut to update Data Modul i.MX8M Mini eDM SBC and DH electronics i.MX8M Plus DHCOM, modeling PMIC to SNVS RTC clock path, dropping QCA clk_out setup, adding bluetooth UART, etc. - A bunch of changes from Peng Fan to add LPSPI, TPM etc for i.MX93, update i.MX8MP/N EVK with UART, I2C addition. - Update cache properties per DeviceTree Specification v0.3. - Add gpio-ranges property for i.MX8DXL and i.MX8Q LSIO Subsystem. - Misc small and random changes. * tag 'imx-dt64-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (60 commits) arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso arm64: dts: imx8mm-evk: add vcc supply for pca6416 arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator arm64: dts: imx8mn-evk: enable uart1 arm64: dts: imx8mn-evk: add i2c gpio recovery settings arm64: dts: imx8mn-evk: set off-on-delay-us in regulator arm64: dts: imx8mn-evk: update vdd_soc dvs voltage arm64: dts: imx8mp-evk: enable I2C2 node arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk arm64: dts: imx8mp-evk: enable uart1/3 ports ARM64: dts: imx8mp-evk: add pwm support arm64: dts: imx8mp: add mlmix power domain arm64: dts: imx8mq: fix dtschema warning for imx7-csi arm64: dts: Update cache properties for freescale arm64: dts: imx8mm-phg: Add initial board support arm64: dts: imx8qxp-ss-lsio: add gpio-ranges property arm64: dts: imx8qm-ss-lsio: add gpio-ranges property arm64: dts: imx8dxl-ss-lsio: add gpio-ranges property arm64: dts: imx8dxl_evk: add lpspi0 support arm64: dts: imx8dxl: add lpspi support ... Link: https://lore.kernel.org/r/20221119125733.32719-5-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'imx-dt-6.2' of ↵Arnd Bergmann26-32/+983
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX arm device tree update for 6.2: - New device tree for Kobo Aura 2 E-Boot reader which is built on i.MX6SL SoC. - Enable backlight and boost support for imx6sl-tolino-shine2hd. - Enable CYTTSP5 touchscreen support for E60K02. - Enable Silergy SY7636A EPD PMIC on imx7d-remarkable2 epaper tablet. - Add watchdog property 'fsl,suspend-in-wait' for i.MX6UL Phytec Phycore SoM to avoid watchdog triggering in 'freeze' low power mode. - Correct the polarity of AT86RF233 reset line for vf610-zii-dev-rev-c board. - A bunch of Colibri device tree updates from Marcel Ziswiler and Philippe Schenker, correct USBH_PEN property, remove spurious debounce property, add USB dual-role switching, and some cosmetic change. - Other small and random changes. * tag 'imx-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: colibri-imx6ull: Enable dual-role switching ARM: dts: imx: e60k02: Add touchscreen ARM: dts: imx6qdl-sabre: Add mmc aliases ARM: dts: imx6ul/ull: suspend i.MX6UL watchdog in wait mode ARM: dts: imx7d-remarkable2: Enable silergy,sy7636a ARM: dts: imx6sl-tolino-shine2hd: Add backlight boost ARM: dts: imx6sl-tolino-shine2hd: Add backlight ARM: dts: colibri-imx7: fix confusing naming ARM: dts: colibri-imx6ull: add -hog to gpio hogs ARM: dts: colibri-imx6ull: enable default peripherals ARM: dts: colibri-imx6ull: keep peripherals disabled ARM: dts: ls1021: correct indentation ARM: dts: vf610-zii-dev-rev-c: fix polarity of at86rf233 reset line ARM: dts: imx7-colibri: remove spurious debounce property ARM: dts: colibri-imx6: specify usbh_pen gpio being active-low ARM: dts: colibri-imx6: move vbus-supply to module level device tree ARM: dts: colibri-imx6: usb dual-role switching ARM: dts: imx: Add devicetree for Kobo Aura 2 Link: https://lore.kernel.org/r/20221119125733.32719-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21x86/pm: Add enumeration check before spec MSRs save/restore setupPawan Gupta1-8/+15
pm_save_spec_msr() keeps a list of all the MSRs which _might_ need to be saved and restored at hibernate and resume. However, it has zero awareness of CPU support for these MSRs. It mostly works by unconditionally attempting to manipulate these MSRs and relying on rdmsrl_safe() being able to handle a #GP on CPUs where the support is unavailable. However, it's possible for reads (RDMSR) to be supported for a given MSR while writes (WRMSR) are not. In this case, msr_build_context() sees a successful read (RDMSR) and marks the MSR as valid. Then, later, a write (WRMSR) fails, producing a nasty (but harmless) error message. This causes restore_processor_state() to try and restore it, but writing this MSR is not allowed on the Intel Atom N2600 leading to: unchecked MSR access error: WRMSR to 0x122 (tried to write 0x0000000000000002) \ at rIP: 0xffffffff8b07a574 (native_write_msr+0x4/0x20) Call Trace: <TASK> restore_processor_state x86_acpi_suspend_lowlevel acpi_suspend_enter suspend_devices_and_enter pm_suspend.cold state_store kernfs_fop_write_iter vfs_write ksys_write do_syscall_64 ? do_syscall_64 ? up_read ? lock_is_held_type ? asm_exc_page_fault ? lockdep_hardirqs_on entry_SYSCALL_64_after_hwframe To fix this, add the corresponding X86_FEATURE bit for each MSR. Avoid trying to manipulate the MSR when the feature bit is clear. This required adding a X86_FEATURE bit for MSRs that do not have one already, but it's a small price to pay. [ bp: Move struct msr_enumeration inside the only function that uses it. ] Fixes: 73924ec4d560 ("x86/pm: Save the MSR validity status at context setup") Reported-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: <stable@kernel.org> Link: https://lore.kernel.org/r/c24db75d69df6e66c0465e13676ad3f2837a2ed8.1668539735.git.pawan.kumar.gupta@linux.intel.com
2022-11-21x86/tsx: Add a feature bit for TSX control MSR supportPawan Gupta2-21/+20
Support for the TSX control MSR is enumerated in MSR_IA32_ARCH_CAPABILITIES. This is different from how other CPU features are enumerated i.e. via CPUID. Currently, a call to tsx_ctrl_is_supported() is required for enumerating the feature. In the absence of a feature bit for TSX control, any code that relies on checking feature bits directly will not work. In preparation for adding a feature bit check in MSR save/restore during suspend/resume, set a new feature bit X86_FEATURE_TSX_CTRL when MSR_IA32_TSX_CTRL is present. Also make tsx_ctrl_is_supported() use the new feature bit to avoid any overhead of reading the MSR. [ bp: Remove tsx_ctrl_is_supported(), add room for two more feature bits in word 11 which are coming up in the next merge window. ] Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: <stable@kernel.org> Link: https://lore.kernel.org/r/de619764e1d98afbb7a5fa58424f1278ede37b45.1668539735.git.pawan.kumar.gupta@linux.intel.com
2022-11-21Revert "arm64/mm: Drop redundant BUG_ON(!pgtable_alloc)"Will Deacon1-1/+3
This reverts commit 9ed2b4616d4e846ece2a04cb5007ce1d1bd9e3f3. Nathan reports early boot failures bisected to this change which look related to the kPTI nG repainting. In any case, consolidating the BUG_ON()s to a single location needs more thought, so revert the change until this is figured out properly. Link: https://lore.kernel.org/r/Y3pS5fdZ3MdLZ00t@dev-arch.thelio-3990X Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2022-11-21arm64: tegra: Remove unneeded clock-names for Tegra132 PWMThierry Reding1-1/+0
There's only a single clock for this IP block, so it doesn't need a clock-names property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234Thierry Reding1-1/+1
The compatible string list for SDHCI on Tegra234 should be "nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci" fallback. Use that consistently for all SDHCI controllers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove unused reset-names for QSPIThierry Reding2-3/+0
The Tegra QSPI controller uses a single reset line, so there's no need for a reset-names property. Remove such properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fixup pinmux node namesThierry Reding5-13/+19
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove reset-names for QSPIThierry Reding1-2/+0
The Tegra QSPI controllers use a single reset control, so reset-names is not necessary and therefore not specified in the DT bindings. Drop the property from device tree files to avoid validation warnings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Use correct compatible string for Tegra234 HDAThierry Reding1-1/+1
The Tegra234 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Use correct compatible string for Tegra194 HDAThierry Reding1-1/+1
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Use vbus-gpios propertyThierry Reding1-2/+2
Instead of using the deprecated vbus-gpio property, switch to using the more standard vbus-gpios property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Restructure Tegra210 PMC pinmux nodesThierry Reding1-21/+19
The PMC pinmux configuration nodes need to be part of a top-level pinmux node. Add that new "pinmux" node and move the configuration nodes into it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Update cache propertiesPierre Gondois3-0/+49
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove 'enable-active-low'Fabio Estevam1-1/+0
The 'enable-active-low' property is not a valid one. Only 'enable-active-high' is valid, and when this property is absent the gpio regulator will act as active low by default. Remove the invalid 'enable-active-low' property. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add dma-channel-mask in GPCDMA nodeAkhil R3-3/+9
Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controllerVidya Sagar1-1/+1
Fix the starting address of the non-prefetchable aperture of PCIe C3 controller. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add missing compatible string to Ethernet USB deviceThierry Reding1-0/+1
According to the DT schema in usb-device.yaml, each USB device node needs a compatible string, so add one for the built-in USB Ethernet device on Jetson TX1. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Separate AON pinmux from main pinmux on Tegra194Thierry Reding1-3/+10
The registers for the AON pinmux reside in a partition different from the registers for the main pinmux. Instead of treating them as one and the same device, split them up so that they are each their own devices. Also add gpio-ranges properties to the corresponding GPIO controllers such that the pinmux and GPIO controllers can be paired up properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add ECAM aperture info for all the PCIe controllersVidya Sagar1-22/+33
Add the ECAM aperture information for all the PCIe controllers of Tegra234. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove clock-names from PWM nodesThierry Reding4-25/+0
The Tegra PWFM controllers use a single clock, so there's no need for a clock-names property. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Enable GTE nodesDipen Patel1-0/+20
Add and enable AON and LIC GTE nodes by default. Signed-off-by: Dipen Patel <dipenp@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Update console for Jetson Xavier and OrinJon Hunter3-3/+3
The Tegra Combined UART (TCU) is the default serial interface for Jetson Xavier and Orin platforms and so update the bootargs for these platforms to use the TCU. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 19:33:18 +0300