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2017-06-15powerpc/64s: Leave interrupts hard enabled in context switch for radixNicholas Piggin2-6/+16
Commit 4387e9ff25 ("[POWERPC] Fix PMU + soft interrupt disable bug") hard disabled interrupts over the low level context switch, because the SLB management can't cope with a PMU interrupt accesing the stack in that window. Radix based kernel mapping does not use the SLB so it does not require interrupts hard disabled here. This is worth 1-2% in context switch performance on POWER9. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-06-15powerpc/64: Avoid restore_math call if possible in syscall exitNicholas Piggin2-19/+47
The syscall exit code that branches to restore_math is quite heavy on Book3S, consisting of 2 mtmsr instructions. Threads that don't use both FP and vector can get caught here if the kernel ever uses FP or vector. Lazy-FP/vec context switching also trips this case. So check for lazy FP and vector before switching RI for restore_math. Move most of this case out of line. For threads that do want to restore math registers, the MSR switches are still suboptimal. Future direction may be to use a soft-RI bit to avoid MSR switches in kernel (similar to soft-EE), but for now at least the no-restore POWER9 context switch rate increases by about 5% due to sched_yield(2) return performance. I haven't constructed a test to measure the syscall cost. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-06-15powerpc/64s: Optimize hypercall/syscall entryNicholas Piggin1-37/+97
After bc3551257a ("powerpc/64: Allow for relocation-on interrupts from guest to host"), a getppid() system call goes from 307 cycles to 358 cycles (+17%) on POWER8. This is due significantly to the scratch SPR used by the hypercall check. It turns out there are a some volatile registers common to both system call and hypercall (in particular, r12, cr0, ctr), which can be used to avoid the SPR and some other overheads. This brings getppid to 320 cycles (+4%). Testing hcall entry performance by running "sc 1" in guest userspace before this patch is 854 cycles, afterwards is 826. Also a small win there. POWER9 syscall is improved by about the same amount, hcall not tested. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-06-15powerpc/mm/radix: Only add X for pages overlapping kernel textMichael Ellerman1-3/+11
Currently we map the whole linear mapping with PAGE_KERNEL_X. Instead we should check if the page overlaps the kernel text and only then add PAGE_KERNEL_X. Note that we still use 1G pages if they're available, so this will typically still result in a 1G executable page at KERNELBASE. So this fix is primarily useful for catching stray branches to high linear mapping addresses. Without this patch, we can execute at 1G in xmon using: 0:mon> m c000000040000000 c000000040000000 00 l c000000040000000 00000000 01006038 c000000040000004 00000000 2000804e c000000040000008 00000000 x 0:mon> di c000000040000000 c000000040000000 38600001 li r3,1 c000000040000004 4e800020 blr 0:mon> p c000000040000000 return value is 0x1 After we get a 400 as expected: 0:mon> p c000000040000000 *** 400 exception occurred Fixes: 2bfd65e45e87 ("powerpc/mm/radix: Add radix callbacks for early init routines") Cc: stable@vger.kernel.org # v4.7+ Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Balbir Singh <bsingharora@gmail.com>
2017-06-15Revert "powerpc: Handle simultaneous interrupts at once"Michael Ellerman1-5/+1
This reverts commit 45cb08f4791ce6a15c54598b4cb73db4b4b8294f. For some reason this is causing IRQ problems on Freescale Book3E machines, eg on my p5020ds: irq 25: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.12.0-rc3-gcc-6.3.1-00037-g45cb08f4791c #624 Call Trace: [c0000000fffdbb10] [c00000000049962c] .dump_stack+0xa8/0xe8 (unreliable) [c0000000fffdbba0] [c0000000000babf4] .__report_bad_irq+0x54/0x140 [c0000000fffdbc40] [c0000000000bb11c] .note_interrupt+0x324/0x380 [c0000000fffdbd00] [c0000000000b7110] .handle_irq_event_percpu+0x68/0x88 [c0000000fffdbd90] [c0000000000b718c] .handle_irq_event+0x5c/0xa8 [c0000000fffdbe10] [c0000000000bc01c] .handle_fasteoi_irq+0xe4/0x298 [c0000000fffdbe90] [c0000000000b59c4] .generic_handle_irq+0x50/0x74 [c0000000fffdbf10] [c0000000000075d8] .__do_irq+0x74/0x1f0 [c0000000fffdbf90] [c0000000000189f8] .call_do_irq+0x14/0x24 [c0000000f7173060] [c0000000000077e4] .do_IRQ+0x90/0x120 [c0000000f7173100] [c00000000001d93c] exc_0x500_common+0xfc/0x100 --- interrupt: 501 at .prepare_to_wait_event+0xc/0x14c LR = .fsl_elbc_run_command+0xc8/0x23c [c0000000f71734d0] [c00000000065f418] .nand_reset+0xb8/0x168 [c0000000f7173560] [c00000000065fec4] .nand_scan_ident+0x2b0/0x1638 [c0000000f7173650] [c000000000666cd8] .fsl_elbc_nand_probe+0x34c/0x5f0 ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300) [c0000000f7173750] [c0000000005a3c60] .platform_drv_probe+0x64/0xb0 [c0000000f71737d0] [c0000000005a12e0] .really_probe+0x290/0x334 [c0000000f7173870] [c0000000005a14a0] .__driver_attach+0x11c/0x120 [c0000000f7173900] [c00000000059e6a0] .bus_for_each_dev+0x98/0xfc [c0000000f71739a0] [c0000000005a0b3c] .driver_attach+0x34/0x4c [c0000000f7173a20] [c0000000005a04b0] .bus_add_driver+0x1ac/0x2e0 [c0000000f7173ac0] [c0000000005a2170] .driver_register+0x94/0x160 [c0000000f7173b40] [c0000000005a3be0] .__platform_driver_register+0x60/0x7c [c0000000f7173bc0] [c000000000d6aab4] .fsl_elbc_nand_driver_init+0x24/0x38 [c0000000f7173c30] [c000000000001934] .do_one_initcall+0x68/0x1b8 [c0000000f7173d00] [c000000000d210f8] .kernel_init_freeable+0x260/0x338 [c0000000f7173db0] [c0000000000021b0] .kernel_init+0x20/0xe70 [c0000000f7173e30] [c0000000000009bc] .ret_from_kernel_thread+0x58/0x9c handlers: [<c000000000ed85c8>] .fsl_lbc_ctrl_irq Disabling IRQ #25 Ben also had concerns with the implementation being potentially slow on some PICs, so revert it for now. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-06-15KVM: PPC: Book3S HV: Preserve userspace HTM state properlyPaul Mackerras1-0/+21
If userspace attempts to call the KVM_RUN ioctl when it has hardware transactional memory (HTM) enabled, the values that it has put in the HTM-related SPRs TFHAR, TFIAR and TEXASR will get overwritten by guest values. To fix this, we detect this condition and save those SPR values in the thread struct, and disable HTM for the task. If userspace goes to access those SPRs or the HTM facility in future, a TM-unavailable interrupt will occur and the handler will reload those SPRs and re-enable HTM. If userspace has started a transaction and suspended it, we would currently lose the transactional state in the guest entry path and would almost certainly get a "TM Bad Thing" interrupt, which would cause the host to crash. To avoid this, we detect this case and return from the KVM_RUN ioctl with an EINVAL error, with the KVM exit reason set to KVM_EXIT_FAIL_ENTRY. Fixes: b005255e12a3 ("KVM: PPC: Book3S HV: Context-switch new POWER8 SPRs", 2014-01-08) Cc: stable@vger.kernel.org # v3.14+ Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-06-15KVM: PPC: Book3S HV: Restore critical SPRs to host values on guest exitPaul Mackerras2-3/+17
This restores several special-purpose registers (SPRs) to sane values on guest exit that were missed before. TAR and VRSAVE are readable and writable by userspace, and we need to save and restore them to prevent the guest from potentially affecting userspace execution (not that TAR or VRSAVE are used by any known program that run uses the KVM_RUN ioctl). We save/restore these in kvmppc_vcpu_run_hv() rather than on every guest entry/exit. FSCR affects userspace execution in that it can prohibit access to certain facilities by userspace. We restore it to the normal value for the task on exit from the KVM_RUN ioctl. IAMR is normally 0, and is restored to 0 on guest exit. However, with a radix host on POWER9, it is set to a value that prevents the kernel from executing user-accessible memory. On POWER9, we save IAMR on guest entry and restore it on guest exit to the saved value rather than 0. On POWER8 we continue to set it to 0 on guest exit. PSPB is normally 0. We restore it to 0 on guest exit to prevent userspace taking advantage of the guest having set it non-zero (which would allow userspace to set its SMT priority to high). UAMOR is normally 0. We restore it to 0 on guest exit to prevent the AMR from being used as a covert channel between userspace processes, since the AMR is not context-switched at present. Fixes: b005255e12a3 ("KVM: PPC: Book3S HV: Context-switch new POWER8 SPRs", 2014-01-08) Cc: stable@vger.kernel.org # v3.14+ Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-06-15ARM: dts: ls1021a: update the clockgen nodeYuantian Tang1-57/+33
qoriq clock driver has been updated to parse the clock configuration information defined in driver itself not in dts. Since the new implementation and the bindings have been merged, it is time to update the clock related node and remove redundent clock configuration information from the dts. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-15ARM: imx_v6_v7_defconfig: Set THERMAL_WRITABLE_TRIPS=y for testingLeonard Crestez1-0/+1
Setting trip points is supported by the imx thermal driver and it is useful to be able to test this without adjusting config. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: sun6i: a31s: primo81: Enable battery power supplyChen-Yu Tsai1-0/+4
The MSI Primo81 tablet has a 3500 mAh 3.7V LiPo battery. Enable the PMIC's battery power supply so the battery can be monitored. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-14ARM: sun6i: a31s: primo81: Change USB OTG to OTG modeChen-Yu Tsai1-2/+14
Now that we have support for the AXP221 PMIC's USB VBUS detection and DRIVEVBUS vbus control, we can use the USB OTG port in proper OTG mode. This patch enables the aforementioned PMIC functions, adds the OTG ID detection pin to the USB PHY node, and changes the mode of USB OTG to "otg". Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-14ARM: sun8i: a83t: Add dt node for the syscon control moduleCorentin Labbe1-0/+6
This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-14Merge branch 'for-upstream' of ↵David S. Miller1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next Johan Hedberg says: ==================== pull request: bluetooth-next 2017-06-14 Here's another batch of Bluetooth patches for the 4.13 kernel: - Fix for Broadcom controllers not supporting Event Mask Page 2 - New QCA ROME USB ID for btusb - Fix for Security Manager Protocol to use constant-time memcmp - Improved support for TI WiLink chips Please let me know if there are any issues pulling. Thanks. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-14ARM64: defconfig: enable meson SPICC as moduleNeil Armstrong1-0/+2
This patch enable the SPI Communications Controller driver as module for the Amlogic platform. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-14ARM64: defconfig: enable IR core, decoders and Meson IR deviceNeil Armstrong1-0/+5
This patch enables the MEDIA Infrared RC Decoders and Meson Infrared decoder for ARM64 defconfig. These drivers are selected as modules by default. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [khilman: make RC_CORE modular too] Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-14ARM: dts: imx6-sabreauto: add the ADV7180 video decoderSteve Longerbeam1-0/+45
Enables the ADV7180 decoder sensor. The ADV7180 connects to the parallel-bus mux input on ipu1_csi0_mux. The ADV7180 power pin is via max7310_b port expander. Changes from Tim Harvey: - Use IRQ_TYPE_LEVEL_LOW instead of 0x8 for interrupt type for clarity. - For 8-bit parallel IPU1-CSI0 bus connection only data[12-19] are used. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6-sabreauto: add pinctrl for gpt input captureSteve Longerbeam1-0/+12
Add pinctrl groups for both GPT input capture channels. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_bSteve Longerbeam1-0/+9
The reset pin to the port expander chip (MAX7310) is controlled by a gpio, so define a reset-gpios property to control it. There are three MAX7310's on the SabreAuto CPU card (max7310_[abc]), but all use the same pin for their reset. Since all can't acquire the same pin, assign it to max7310_b, that chip is needed by more functions (usb and adv7180). Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6-sabreauto: create i2cmux for i2c3Steve Longerbeam1-21/+44
The sabreauto uses a steering pin to select between the SDA signal on i2c3 bus, and a data-in pin for an SPI NOR chip. Use i2cmux to control this steering pin. Idle state of the i2cmux selects SPI NOR. This is not a classic way to use i2cmux, since one side of the mux selects something other than an i2c bus, but it works and is probably the cleanest solution. Note that if one thread is attempting to access SPI NOR while another thread is accessing i2c3, the SPI NOR access will fail since the i2cmux has selected the SDA pin rather than SPI NOR data-in. This couldn't be avoided in any case, the board is not designed to allow concurrent i2c3 and SPI NOR functions (and the default device-tree does not enable SPI NOR anyway). Devices hanging off i2c3 should now be defined under i2cmux, so that the steering pin can be properly controlled to access those devices. The port expanders (MAX7310) are thus moved into i2cmux. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensorsSteve Longerbeam3-1/+123
Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor. The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux. The OV5640 connects to the input port on the MIPI CSI-2 receiver on mipi_csi. Until the OV5652 sensor module compatible with the SabreSD becomes available for testing, the ov5642 node is currently disabled. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensorsSteve Longerbeam3-0/+158
Adds the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor. Both hang off the same i2c2 bus, so they require different (and non- default) i2c slave addresses. The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux. The OV5640 connects to the input port on the MIPI CSI-2 receiver on mipi_csi. The OV5642 node is disabled temporarily while the subdev driver is cleaned up and submitted later. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6qdl-sabrelite: remove erratum ERR006687 workaroundSteve Longerbeam1-4/+0
There is a pin conflict with GPIO_6. This pin functions as a power input pin to the OV5642 camera sensor, but ENET uses it as the h/w workaround for erratum ERR006687, to wake-up the ARM cores on normal RX and TX packet done events. So we need to remove the h/w workaround to support the OV5642. The result is that the CPUidle driver will no longer allow entering the deep idle states on the sabrelite. This is a partial revert of commit 6261c4c8f13e ("ARM: dts: imx6qdl-sabrelite: use GPIO_6 for FEC interrupt.") commit a28eeb43ee57 ("ARM: dts: imx6: tag boards that have the HW workaround for ERR006687") Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6qdl: add capture-subsystem deviceSteve Longerbeam2-0/+10
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6qdl: Add video multiplexers, mipi_csi, and their connectionsPhilipp Zabel3-0/+290
This patch adds the device tree graph connecting the input multiplexers to the IPU CSIs and the MIPI-CSI2 gasket on i.MX6. The MIPI_IPU multiplexers are added as children of the iomuxc-gpr syscon device node. On i.MX6Q/D two two-input multiplexers in front of IPU1 CSI0 and IPU2 CSI1 allow to select between CSI0/1 parallel input pads and the MIPI CSI-2 virtual channels 0/3. On i.MX6DL/S two five-input multiplexers in front of IPU1 CSI0 and IPU1 CSI1 allow to select between CSI0/1 parallel input pads and any of the four MIPI CSI-2 virtual channels. Changes from Steve Longerbeam: - Removed some dangling/unused endpoints (ipu2_csi0_from_csi2ipu) - Renamed the mipi virtual channel endpoint labels, from "mipi_csiX_..." to "mipi_vcX...". - Added input endpoint anchors to the video muxes for the connections from parallel sensors. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 nodeSteve Longerbeam1-0/+7
Add to the MIPI CSI2 receiver node: compatible strings, interrupt sources, and clocks. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14ARM: dts: imx6qdl: add multiplexer controlsPhilipp Zabel3-1/+26
The IOMUXC General Purpose Register space contains various bitfields that control video bus multiplexers. Describe them using a mmio-mux node. The placement of the IPU CSI video mux controls differs between i.MX6D/Q and i.MX6S/DL. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14arm64: dts: ls1088a: update sata nodeYuantian Tang1-2/+2
1. Remove ls1043a compatible string from node 2. Fix the sata ecc register address error Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-06-14s390/ipl: revert Load Normal semantics for LPAR CCW-type re-IPLHeiko Carstens1-6/+1
This reverts the two commits 7afbeb6df2aa ("s390/ipl: always use load normal for CCW-type re-IPL") 0f7451ff3ab8 ("s390/ipl: use load normal for LPAR re-ipl") The two commits did not take into account that behavior of standby memory changes fundamentally if the re-IPL method is changed from Load Clear to Load Normal. In case of the old re-IPL clear method all memory that was initially in standby state will be put into standby state again within the re-IPL process. Or in other words: memory that was brought online before a re-IPL will be offline again after a reboot. Given that we use different re-IPL methods depending on the hypervisor and CCW-type vs SCSI re-IPL it is not easy to tell in advance when and why memory will stay online or will be offline after a re-IPL. This does also have other side effects, since memory that is online from the beginning will be in ZONE_NORMAL by default vs ZONE_MOVABLE for memory that is offline. Therefore, before the change, a user could online and offline memory easily since standby memory was always in ZONE_NORMAL. After the change, and a re-IPL, this depended on which memory parts were online before the re-IPL. From a usability point of view the current behavior is more than suboptimal. Therefore revert these changes until we have a better solution and get back to a consistent behavior. The bad thing about this is that the time required for a re-IPL will be significantly increased for configurations with several 100GB or 1TB of memory. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2017-06-14clocksource/drivers: Rename CLKSRC_OF to TIMER_OFDaniel Lezcano11-16/+16
The config option name is now renamed to 'TIMER_OF' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-14clocksource/drivers: Rename clocksource_probe to timer_probeDaniel Lezcano23-27/+27
The function name is now renamed to 'timer_probe' for consistency with the CLOCKSOURCE_OF_DECLARE => TIMER_OF_DECLARE change. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-14clocksource/drivers: Rename CLOCKSOURCE_OF_DECLARE to TIMER_OF_DECLAREDaniel Lezcano4-6/+6
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-14arm: mach-rpc: ecard: fix build errorGreg Kroah-Hartman1-1/+1
The last commit from me had a missing ';' which broke the build. Thanks to Arnd for pointing out the issue. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-14arm64: dts: r8a7796: Add reset control properties for audioGeert Uytterhoeven1-0/+10
Note that the audio module has resets for the Serial Sound Interfaces only. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-06-14arm64: dts: r8a7795: Add reset control properties for audioGeert Uytterhoeven1-0/+10
Note that the audio module has resets for the Serial Sound Interfaces only. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-06-14ARM: shmobile: pm-rmobile: Use GENPD_FLAG_ALWAYS_ONGeert Uytterhoeven1-15/+4
Improve handling of always-on PM domains by using the GENPD_FLAG_ALWAYS_ON flag introduced in commit ffaa42e8a40b7f10 ("PM / Domains: Enable users of genpd to specify always on PM domains"). Note that the PM domain containing the serial console is still handled locally. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-06-14ARM: OMAP4: hwmod_data: add SHAM crypto acceleratorTero Kristo1-0/+36
OMAP4 SoC contains SHAM crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-14ARM: OMAP4: hwmod data: add desSebastian Reichel1-0/+37
This fixes the following error during kernel boot: platform 480a5000.des: Cannot lookup hwmod 'des' Unfortunately the DES module is only documented partly in the OMAP4430 TRM. I found an old patch from Joel, which I took over and updated for currently mainline. Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-14ARM: OMAP4: hwmod data: add aes2Sebastian Reichel1-0/+22
This adds the hwmod entry for the second AES module available on OMAP4. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-14ARM: OMAP4: hwmod data: add aes1Sebastian Reichel1-0/+41
This fixes the following error during kernel boot: platform 4b501000.aes: Cannot lookup hwmod 'aes1' Unfortunately the AES module is only documented partly in the OMAP4430 TRM. I found an old patch from Joel, which I took over and updated for currently mainline. Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-14ARM: dts: omap4: add SHAM nodeTero Kristo1-0/+9
Add SHAM crypto accelerator. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-14ARM: dts: omap4: add aes2 instanceTero Kristo1-0/+9
OMAP4 has AES2 instance, so add its integration data under DT. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-14ARM: dts: omap4.dtsi: remove aes[12]_fckSebastian Reichel1-16/+0
"aes1_fck" and "aes2_fck" are controlled by hwmod. Drop clock entries to avoid conflicts. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-14ARM: dts: omap4: Fix aes entrySebastian Reichel1-2/+2
OMAP4 has a second aes module, so let's use proper name for the first instance. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-14ARM: pxa: Delete an error message for a failed memory allocation in ↵Markus Elfring1-3/+1
pxa3xx_u2d_probe() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2017-06-14ARM: pxa: Improve a size determination in pxa3xx_u2d_probe()Markus Elfring1-1/+1
Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2017-06-14ARM: pxa: Delete an error message for a failed memory allocation in ↵Markus Elfring1-3/+1
pxa_pm_init() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2017-06-14ARM: pxa: magician: Add support for ADS7846 touchscreenPetr Cvek2-1/+84
This patch adds a support for ADS7846 touchscreen driver. The basic functionality was tested, x_plate_ohms and y_plate_ohms were physically measured. The value pressure_max was empirically set to match the measured range, which is affected by x_plate_ohms and ADS samples. The value of keep_vref_on should be set. A tested model (T-Mobile MDA Compact PM10A) doesn't seem to use Vref pin as the input from an external source. On this model the unset keep_vref_on cause high jitter of measured values. SPI framing pin (gpio_cs) must be used in GPIO mode due to an incompatible autoframing of PXA27x controller and ADS7846 device. Signed-off-by: Petr Cvek <petr.cvek@tul.cz> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2017-06-14x86/mce: Update bootlog description to reflect behavior on AMDYazen Ghannam1-2/+3
The bootlog option is only disabled by default on AMD Fam10h and older systems. Update bootlog description to say this. Change the family value to hex to avoid confusion. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/20170613162835.30750-9-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-06-14x86/mce: Don't disable MCA banks when offlining a CPU on AMDYazen Ghannam1-2/+3
AMD systems have non-core, shared MCA banks within a die. These banks are controlled by a master CPU per die. If this CPU is offlined then all the shared banks are disabled in addition to the CPU's core banks. Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared between SMT thread siblings. If a CPU is offlined then all its sibling's MCA banks are also disabled. Extend the existing vendor check to AMD too. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> [ Fix up comment. ] Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/20170613162835.30750-8-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-06-14x86/mce/mce-inject: Preset the MCE injection structBorislav Petkov1-0/+9
Populate the MCE injection struct before doing initial injection so that values which don't change have sane defaults. Tested-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Yazen Ghannam <yazen.ghannam@amd.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/20170613162835.30750-7-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 23:08:17 +0300