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2025-05-09arm64: dts: freescale: imx93-phyboard-segin: Fix SD-card pinctrlPrimoz Fiser1-5/+5
Until now, all usdhc2 (SD-card) pinctrl labels pointed to one pinctrl group "usdhc2grp" which was overwritten twice by the 100 and 200 MHz modes. Fix this by using unique pinctrl names. Additionally, adjust MX93_PAD_SD2_CLK__USDHC2_CLK pad drive-strength according to values obtained by measurements from the PHYTEC hardware department to improve signal integrity. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx93-phyboard-segin: Disable SD-card write-protectPrimoz Fiser1-0/+1
Add disable-wp flag (write-protect) to usdhc2 node (SD-card) to get rid of the following kernel boot warning: host does not support reading read-only switch, assuming write-enable Micro SD cards can't be physically write-protected like full-sized cards anyways. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx93-phyboard-segin: Drop eMMC no-1-8-v flagPrimoz Fiser1-5/+0
Drop redundant 'no-1-8-v' flag from usdhc1 (eMMC) node. Flag is now set by default in the SOM include file (imx93-phycore-som.dtsi). Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx93-phycore-som: Add eMMC no-1-8-v by defaultPrimoz Fiser1-0/+1
The phyCORE-i.MX93 SoM comes in two variants, one with VDD_IO set to 3.3V and the other variant to 1.8V. The 3.3V variant can only support DDR52 mode, while 1.8V variant is capable of HS400ES eMMC mode. The information about VDD_IO option is encoded in the SoM's EEPROM. EEPROM is read in the bootloader and bootloader clears the "no-1-8-v" flag in case of 1.8V SoM variant is detected. Thus add property 'no-1-8-v' by default to usdhc1 (eMMC) node and let bootloader handle the flag. In case EEPROM is erased or read-out fails, flag "no-1-8-v" also ensures fall-back compatibility with both SoM variants. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx93-phycore-som: Enhance eMMC pinctrlPrimoz Fiser1-10/+47
Improve eMMC on phyCORE-i.MX93 SOM by adding 100MHz and 200MHz pinctrl modes. This enables to use eMMC at enhanced data rates (e.g. HS400). While at it, apply a workaround for the i.MX93 chip errata ERR052021. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx93-phycore-som: Disable LED pull-upPrimoz Fiser1-1/+1
There is already an external pull-down resistor on the LED output line. It makes no sense to have both pull-down and pull-up resistors enabled at the same time. Thus disable the internal pull-up. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx93-phycore-som: Add EEPROM supportPrimoz Fiser1-0/+8
Add support for the EEPROM chip available on I2C3 bus (address 0x50), used for the PHYTEC SOM detection. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx93-phycore-som: Add PMIC supportPrimoz Fiser1-0/+97
PMIC driver for PCA9451A used on phyCORE-i.MX93 SOM is available since commit 5edeb7d31262 ("regulator: pca9450: add pca9451a support"). Add support for it in the SOM device-tree. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: imx8mp: use 800MHz NoC OPP for nominal drive modeAhmad Fatoum2-0/+8
When running in nominal drive mode, the maximum allowed frequency for the NoC is 800MHz, but the OPP table for the i.MX8MP interconnect device listed the 1GHz operating point for the NoC, regardless of the active mode. The newly introduced imx8mp-nominal.dtsi header reconfigures the clock controller to observe nominal drive mode limits, so have it modify the maximum NoC OPP as well. Fixes: 255fbd9eabe7 ("arm64: dts: imx8mp: Add optional nominal drive mode DTSI") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: add imx8mp-libra-rdk-fpsc LVDS panel overlayYannic Moog2-0/+46
The Libra board has an LVDS connector. Add an overlay for an etml1010g3dra LVDS panel supported for the phyCORE-i.MX 8M Plus that may be connected to it. Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: add imx8mp-libra-rdk-fpsc boardYannic Moog3-0/+1087
Add device tree for the Libra-i.MX 8M Plus FPSC board. The Libra is a pure development board and has hardware to support FPSC-24-A.0 set of features. It can be populated with the phyCORE-i.MX 8M Plus SoM to form a SBC. The phyCORE-i.MX 8M Plus FPSC [1] SoM uses only a subset of the hardware features the Libra board provides. The phyCORE-i.MX8MP FPSC itself is a System on Module based on the i.MX 8M Plus SoC utilizing the Future Proof Solder Core [2] standard. To be able to easily map FPSC interface names to SoC interfaces, the FPSC interface names are added as inline comments. Example: &i2c5 { /* FPSC I2C4 */ pinctrl-0 = <&pinctrl_i2c5>; [...] }; Here, I2C4 is the FPSC interface name. The i2c5 instance of the i.MX 8M Plus SoC is used to fulfill the i2c functionality and its signals are routed to the FPSC I2C4 signal pins: pinctrl_i2c5: i2c5grp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 /* I2C4_SDA */ MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 /* I2C4_SCL */ >; }; The features are almost identical to the existing phyCORE-i.MX 8M Plus SoM (dts: imx8mp-phycore-som.dtsi), but the pin muxing is different due to the FPSC standard as well as 1.8V IO voltage instead of 3.3V. [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc/ Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09x86/tdx: tdx_mcall_get_report0: Return -EBUSY on TDCALL_OPERAND_BUSY errorCedric Xing1-5/+8
Return `-EBUSY` from tdx_mcall_get_report0() when `TDG.MR.REPORT` returns `TDCALL_OPERAND_BUSY`. This enables the caller to retry obtaining a TDREPORT later if another VCPU is extending an RTMR concurrently. Signed-off-by: Cedric Xing <cedric.xing@intel.com> Acked-by: Dionna Amalie Glaze <dionnaglaze@google.com> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://patch.msgid.link/20250506-tdx-rtmr-v6-4-ac6ff5e9d58a@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2025-05-09x86/tdx: Add tdx_mcall_extend_rtmr() interfaceCedric Xing3-0/+40
The TDX guest exposes one MRTD (Build-time Measurement Register) and four RTMR (Run-time Measurement Register) registers to record the build and boot measurements of a virtual machine (VM). These registers are similar to PCR (Platform Configuration Register) registers in the TPM (Trusted Platform Module) space. This measurement data is used to implement security features like attestation and trusted boot. To facilitate updating the RTMR registers, the TDX module provides support for the `TDG.MR.RTMR.EXTEND` TDCALL which can be used to securely extend the RTMR registers. Add helper function to update RTMR registers. It will be used by the TDX guest driver in enabling RTMR extension support. Co-developed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Cedric Xing <cedric.xing@intel.com> Acked-by: Dionna Amalie Glaze <dionnaglaze@google.com> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://patch.msgid.link/20250506-tdx-rtmr-v6-3-ac6ff5e9d58a@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2025-05-09arm64: tegra: Wire up CEC to devkitsAaron Kling6-0/+36
This enables HDMI CEC and routes it to the HDMI port on all supported Tegra210, Tegra186, and Tegra194 devkits. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-4-b6337b66ccad@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-09arm64: tegra: Add CEC controller on Tegra210Aaron Kling1-0/+9
The CEC controller found on Tegra210 can be used to control consumer devices using the HDMI CEC pin. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-3-b6337b66ccad@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-09arm64: tegra: Add fallback CEC compatiblesAaron Kling2-2/+2
The tegra_cec driver only declares support up to Tegra210 and will not declare support for Tegra186 or Tegra194. Thus list a fallback compatible for these chips to tegra210-cec as they work as-is with the existing driver. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250413-tegra-cec-v4-2-b6337b66ccad@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-09ARM: tegra: apalis-eval: Remove pcie-switch nodeFrancesco Dolcini4-20/+0
The compatible "plx,pex8605" does not exist, there is no DT binding for it and there was never a driver matching this compatible, remove it. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250410063919.11199-1-francesco@dolcini.it Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-09arm64: tegra: Add uartd serial alias for Jetson TX1 moduleAaron Kling1-0/+1
If a serial-tegra interface does not have an alias, the driver fails to probe with an error: serial-tegra 70006300.serial: failed to get alias id, errno -19 This prevents the bluetooth device from being accessible. Fixes: 6eba6471bbb7 ("arm64: tegra: Wire up Bluetooth on Jetson TX1 module") Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Tomasz Maciej Nowak <tmn505@gmail.com> Link: https://lore.kernel.org/r/20250420-tx1-bt-v1-1-153cba105a4e@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-09arm64: tegra: Bump #address-cells and #size-cells on Tegra186Aaron Kling1-67/+67
This was done for Tegra194 and Tegra234 in 2838cfd, but Tegra186 was not part of that change. The same reasoning for that commit also applies to Tegra186, plus keeping the archs as close to each other as possible makes it easier to compare between them and support features concurrently. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250419-tegra186-host1x-addr-size-v1-1-a7493882248d@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-09arm64: tegra: p2180: Explicitly enable GPUAaron Kling1-0/+1
The gpu node originally was explicitly left disabled as it was expected for the bootloader to enable it. However, this is only done in u-boot. If u-boot is not in the boot chain, this will never be enabled. Other Tegra210 devices already explicitly enable the gpu, so make p2180 match. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250420-tx1-gpu-v1-1-d500de18e43e@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: p3310: Explicitly enable GPUAaron Kling1-0/+4
The gpu node originally was explicitly left disabled as it was expected for the bootloader to enable it. However, this is only done in U-Boot. If U-Boot is not in the boot chain, this will never be enabled. Other Tegra186 devices already explicitly enable the GPU, so make p3310 match. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250426-tx2-gpu-v1-1-fa1c78dcdbdc@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Add DMA properties for Tegra186 and Tegra194 UARTsAaron Kling6-0/+38
Adding the missing dmas and dma-names properties which are required for uart when using with the Tegra HSUART driver. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250428-tegra-serial-fixes-v1-2-4f47c5d85bf6@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Drop remaining serial clock-names and reset-namesAaron Kling2-24/+0
The referenced commit only removed some of the names, missing all that weren't in use at the time. The commit removes the rest. Fixes: 71de0a054d0e ("arm64: tegra: Drop serial clock-names and reset-names") Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250428-tegra-serial-fixes-v1-1-4f47c5d85bf6@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Enable PWM fan on the Jetson TX2 DevkitAaron Kling1-0/+109
This is based on the existing configuration of the Jetson TX2 NX devkit. The fan and thermal characteristics of the two devkits are similar, so using the same configuration. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250427-tx2-therm-v1-1-65ddb4314723@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Enable PWM fan on the Jetson TX1 DevkitAaron Kling1-0/+75
This is based on 6f78a94, which enabled added the fan and thermal zones for the Jetson Nano Devkit. The fan and thermal characteristics of the two devkits are similar, so using the same configuration. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://lore.kernel.org/r/20250501-tx1-therm-v2-1-abdb1922c001@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08ARM: tegra: Add device-tree for ASUS Transformer Pad LTE TF300TLSvyatoslav Ryhel2-0/+858
Add device-tree for ASUS Transformer Pad LTE TF300TL, which is NVIDIA Tegra30-based tablet device. Co-developed-by: Ion Agorria <ion@agorria.com> Signed-off-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Link: https://lore.kernel.org/r/20250503102950.32744-4-clamor95@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Add I2C aliases for Tegra234Akhil R1-0/+12
Add aliases for all I2C nodes so that the I2C devnode numbers align with hardware bus number. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Link: https://lore.kernel.org/r/20250506095936.10687-4-akhilrajeev@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08arm64: tegra: Configure QSPI clocks and add DMAVishwaroop A1-0/+10
For Tegra234 devices, set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to 99.99 MHz using PLLC as the parent clock. These frequencies enable Quad IO reads at up to 99.99 MHz, the maximum achievable given PLL and clock divider limitations. Introduce IOMMU property which is needed for internal DMA transfers. Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://lore.kernel.org/r/20250506152350.3370291-2-va@nvidia.com Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08ARM: tegra: Rename the apbdma nodename to match with common dma-controller ↵Charan Pedumuru2-2/+2
binding Rename the apbdma nodename from "dma@" to "dma-controller@" to align with linux common dma-controller binding. Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20250507-nvidea-dma-v4-1-6161a8de376f@gmail.com [treding@nvidia.com: adjust subject prefix for consistency] Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-05-08ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable USB host portWolfram Sang1-0/+4
Can be used via the USB connector J20. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250508074311.20343-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08ARM: dts: renesas: r9a06g032-rzn1d400-db: Add pinmux for the CPLDWolfram Sang1-0/+10
The CPLD has no dedicated driver, so apply the pinmux settings with the pinmux driver instead. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250508074311.20343-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08arm64: dts: renesas: white-hawk-single: Improve Ethernet TSN descriptionGeert Uytterhoeven1-2/+6
- Add the missing "ethernet3" alias for the Ethernet TSN port, so U-Boot will fill its local-mac-address property based on the "eth3addr" environment variable (if set), avoiding a random MAC address being assigned by the OS, - Rename the numerical Ethernet PHY label to "tsn0_phy", to avoid future conflicts, and for consistency with the "avbN_phy" labels. Fixes: 3d8e475bd7a724a9 ("arm64: dts: renesas: white-hawk-single: Wire-up Ethernet TSN") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/367f10a18aa196ff1c96734dd9bd5634b312c421.1746624368.git.geert+renesas@glider.be
2025-05-08ARM: dts: renesas: r9a06g032-rzn1d400-db: Enable USB device portWolfram Sang1-0/+4
Can be used via the microUSB connector CN9. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250425100129.11942-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08ARM: dts: renesas: r9a06g032-rzn1d400-eb: Describe 9-pin D-sub serial portWolfram Sang1-0/+15
A simple CTS/RTS capable UART on a good old D-sub connector. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424102805.22803-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08arm64: dts: renesas: beacon-renesom: Align wifi node name with bindingsKrzysztof Kozlowski1-1/+1
Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: r8a774a1-beacon-rzg2m-kit.dtb: bcrmf@1: $nodename:0: 'bcrmf@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424084748.105255-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08arm64: dts: renesas: rzg2l-smarc: Enable GPT on carrier boardBiju Das4-0/+27
The GPT4 IOs are available on the carrier board's PMOD0 connector (J1). Enable the GPT on the carrier board by adding the GPT pinmux and node on the carrier board dtsi file. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424054050.28310-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08arm64: dts: renesas: r9a07g054: Add GPT supportBiju Das1-0/+115
Add GPT support by adding pwm node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424054050.28310-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08arm64: dts: renesas: r9a07g044: Add GPT supportBiju Das1-0/+115
Add GPT support by adding pwm node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424054050.28310-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08arm64: dts: renesas: sparrow-hawk: Add MSIOF Sound supportKuninori Morimoto1-0/+106
Sparrow Hawk has Headset (CONN3) AUX_IN (CONN4) for Sound input/output which is using MSIOF. Support it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/87plha2wzr.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/874ixxcg3w.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08ARM: dts: renesas: r9a06g032-rzn1d400-eb: Add GMAC1 portWolfram Sang1-0/+65
This port bypasses the switch and is directly connected to the GMAC. Co-developed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250414100206.7185-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-08Merge patch series "riscv: Add vendor extensions support for SiFive"Palmer Dabbelt11-1/+117
Cyan Yang <cyan.yang@sifive.com> says: This patch set adds four vendor-specific ISA extensions from SiFive: "xsfvqmaccdod", "xsfvqmaccqoq", "xsfvfnrclipxfqf", and "xsfvfwmaccqqq". Additionally, a new hwprobe key, RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0, has been added to query which SiFive vendor extensions are supported on the current platform. Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-1-cyan.yang@sifive.com * b4-shazam-merge: riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension riscv: hwprobe: Document SiFive xsfvfwmaccqqq vendor extension riscv: Add SiFive xsfvfwmaccqqq vendor extension dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension riscv: hwprobe: Document SiFive xsfvfnrclipxfqf vendor extension riscv: Add SiFive xsfvfnrclipxfqf vendor extension dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq riscv: hwprobe: Document SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-05-08riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extensionCyan Yang2-0/+2
Add hwprobe for SiFive "xsfvfwmaccqqq" vendor extension. Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-13-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-05-08riscv: Add SiFive xsfvfwmaccqqq vendor extensionCyan Yang2-0/+2
Add SiFive vendor extension "xsfvfwmaccqqq" support to the kernel. Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-11-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-05-08riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extensionCyan Yang2-0/+2
Add hwprobe for SiFive "xsfvfnrclipxfqf" vendor extension. Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-9-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-05-08riscv: Add SiFive xsfvfnrclipxfqf vendor extensionCyan Yang2-0/+2
Add SiFive vendor extension "xsfvfnrclipxfqf" support to the kernel. Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-7-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-05-08riscv: hwprobe: Add SiFive vendor extension support and probe for ↵Cyan Yang6-0/+50
xsfqmaccdod and xsfqmaccqoq Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0" which allows userspace to probe for the new vendor extensions from SiFive. Also, add new hwprobe for SiFive "xsfvqmaccdod" and "xsfvqmaccqoq" vendor extensions. Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-5-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-05-08riscv: hwprobe: Document SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensionsCyan Yang2-1/+2
Document the support for sifive vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 and two vendor extensions for SiFive Int8 Matrix Multiplication Instructions using RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD and RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ. Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-4-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-05-08riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensionsCyan Yang5-0/+57
Add SiFive vendor extension support to the kernel with the target of "xsfvqmaccdod" and "xsfvqmaccqoq". Signed-off-by: Cyan Yang <cyan.yang@sifive.com> Link: https://lore.kernel.org/r/20250418053239.4351-3-cyan.yang@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-05-08treewide, timers: Rename try_to_del_timer_sync() as timer_delete_sync_try()Ingo Molnar1-1/+1
Move this API to the canonical timer_*() namespace. Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250507175338.672442-9-mingo@kernel.org
2025-05-08timers: Rename NEXT_TIMER_MAX_DELTA as TIMER_NEXT_MAX_DELTAIngo Molnar1-4/+4
Move this macro to the canonical TIMER_* namespace. Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250507175338.672442-7-mingo@kernel.org
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 08:48:50 +0300