Age | Commit message (Expand) | Author | Files | Lines |
2020-07-02 | perf/x86: Add constraint to create guest LBR event without hw counter | Like Xu | 1 | -0/+4 |
2020-07-02 | perf/x86/lbr: Add interface to get LBR information | Like Xu | 1 | -0/+20 |
2020-02-11 | perf/x86/intel: Output LBR TOS information correctly | Kan Liang | 1 | -3/+9 |
2020-02-11 | perf/core: Add new branch sample type for HW index of raw branch records | Kan Liang | 1 | -0/+3 |
2019-10-28 | perf/x86/intel: Implement LBR callstack context synchronization | Alexey Budankov | 1 | -0/+23 |
2019-09-03 | perf/x86: Make more stuff static | Valdis Klētnieks | 1 | -1/+1 |
2019-04-16 | perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them | Andi Kleen | 1 | -1/+12 |
2019-04-16 | perf/x86/intel: Support adaptive PEBS v4 | Kan Liang | 1 | -0/+22 |
2019-01-29 | x86/events: Mark expected switch-case fall-throughs | Gustavo A. R. Silva | 1 | -0/+1 |
2018-09-10 | perf/x86/intel: Add support/quirk for the MISPREDICT bit on Knights Landing CPUs | Jacek Tomaka | 1 | -0/+4 |
2018-06-21 | perf/x86/intel/lbr: Optimize context switches for the LBR call stack | Kan Liang | 1 | -1/+23 |
2018-06-21 | perf/x86/intel/lbr: Fix incomplete LBR call stack | Kan Liang | 1 | -6/+26 |
2018-02-15 | x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping | Jia Zhang | 1 | -1/+1 |
2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman | 1 | -0/+1 |
2017-07-30 | Merge branch 'perf/urgent' into perf/core, to pick up latest fixes and refres... | Ingo Molnar | 1 | -0/+4 |
2017-07-21 | perf/x86/intel: Add proper condition to run sched_task callbacks | Jiri Olsa | 1 | -0/+4 |
2017-07-19 | perf/x86/intel: Record branch type | Jin Yao | 1 | -1/+51 |
2017-06-30 | perf/x86/intel: Constify the 'lbr_desc[]' array and make a function static | Colin Ian King | 1 | -2/+2 |
2017-04-14 | perf/x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32() | Peter Zijlstra | 1 | -0/+3 |
2016-10-16 | perf/x86/intel: Remove an inconsistent NULL check | Dan Carpenter | 1 | -2/+2 |
2016-08-10 | perf/x86/intel: Clean up LBR state tracking | Peter Zijlstra | 1 | -28/+29 |
2016-08-10 | perf/x86/intel: Remove redundant test from intel_pmu_lbr_add() | Peter Zijlstra | 1 | -2/+1 |
2016-08-10 | perf/x86/intel: Eliminate dead code in intel_pmu_lbr_del() | Peter Zijlstra | 1 | -6/+0 |
2016-08-10 | perf/x86: Ensure perf_sched_cb_{inc,dec}() is only called from pmu::{add,del}() | Peter Zijlstra | 1 | -2/+2 |
2016-07-07 | perf/x86/intel: Fix rdlbr_to() MSR reading typo | Peter Zijlstra | 1 | -1/+1 |
2016-06-27 | perf/x86/intel: Add {rd,wr}lbr_{to,from} wrappers | Peter Zijlstra | 1 | -13/+40 |
2016-06-27 | perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switch | David Carrillo-Cisneros | 1 | -3/+21 |
2016-06-27 | perf/x86/intel: Fix trivial formatting and style bug | David Carrillo-Cisneros | 1 | -3/+3 |
2016-06-27 | perf/x86/intel: Fix MSR_LAST_BRANCH_FROM_x bug when no TSX | David Carrillo-Cisneros | 1 | -0/+52 |
2016-06-27 | perf/x86/intel: Print LBR support statement after validation | David Carrillo-Cisneros | 1 | -9/+0 |
2016-04-28 | Merge branch 'perf/urgent' into perf/core, to resolve conflict | Ingo Molnar | 1 | -2/+4 |
2016-04-28 | perf/x86/intel: Fix incorrect lbr_sel_mask value | Kan Liang | 1 | -2/+4 |
2016-04-23 | perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUs | Kan Liang | 1 | -0/+18 |
2016-04-23 | perf/x86/intel: Add Goldmont CPU support | Kan Liang | 1 | -1/+12 |
2016-03-17 | Merge branch 'x86/cleanups' into x86/urgent | Ingo Molnar | 1 | -1/+1 |
2016-02-17 | perf/x86: Move perf_event.h to its new home | Borislav Petkov | 1 | -1/+1 |
2016-02-17 | perf/x86: Move perf_event_intel_lbr.c ........ => x86/events/intel/lbr.c | Borislav Petkov | 1 | -0/+1062 |