Age | Commit message (Expand) | Author | Files | Lines |
2019-05-30 | treewide: Add SPDX license identifier - Kbuild | Greg Kroah-Hartman | 2 | -0/+2 |
2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner | 3 | -27/+3 |
2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 | Thomas Gleixner | 1 | -9/+1 |
2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 | Thomas Gleixner | 1 | -5/+1 |
2019-05-24 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120 | Thomas Gleixner | 5 | -70/+5 |
2019-05-24 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 36 | Thomas Gleixner | 1 | -5/+1 |
2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner | 6 | -0/+6 |
2019-05-19 | Merge tag 'kbuild-v5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ma... | Linus Torvalds | 1 | -4/+0 |
2019-05-19 | Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds | 34 | -320/+584 |
2019-05-18 | arch: remove dangling asm-generic wrappers | Masahiro Yamada | 1 | -4/+0 |
2019-05-17 | riscv: fix locking violation in page fault handler | Andreas Schwab | 1 | -1/+2 |
2019-05-17 | RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs | Yash Shah | 3 | -0/+192 |
2019-05-17 | RISC-V: Avoid using invalid intermediate translations | Palmer Dabbelt | 1 | -2/+10 |
2019-05-17 | riscv: Support BUG() in kernel module | Vincent Chen | 1 | -1/+1 |
2019-05-17 | riscv: Add the support for c.ebreak check in is_valid_bugaddr() | Vincent Chen | 2 | -4/+23 |
2019-05-17 | riscv: support trap-based WARN() | Vincent Chen | 1 | -10/+18 |
2019-05-17 | riscv: fix sbi_remote_sfence_vma{,_asid}. | Gary Guo | 1 | -7/+12 |
2019-05-17 | riscv: move switch_mm to its own file | Gary Guo | 3 | -52/+72 |
2019-05-17 | riscv: move flush_icache_{all,mm} to cacheflush.c | Gary Guo | 3 | -50/+62 |
2019-05-17 | RISC-V: Access CSRs using CSR numbers | Anup Patel | 9 | -48/+57 |
2019-05-17 | RISC-V: Add interrupt related SCAUSE defines in asm/csr.h | Anup Patel | 2 | -16/+21 |
2019-05-17 | RISC-V: Use tabs to align macro values in asm/csr.h | Anup Patel | 1 | -38/+38 |
2019-05-17 | RISC-V: Fix minor checkpatch issues. | Atish Patra | 1 | -2/+2 |
2019-05-17 | RISC-V: Support nr_cpus command line option. | Atish Patra | 1 | -1/+9 |
2019-05-14 | riscv: switch over to generic free_initmem() | Mike Rapoport | 1 | -5/+0 |
2019-05-08 | Merge tag 'audit-pr-20190507' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Linus Torvalds | 1 | -1/+1 |
2019-05-07 | Merge tag 'arm64-mmiowb' of git://git.kernel.org/pub/scm/linux/kernel/git/arm... | Linus Torvalds | 3 | -13/+17 |
2019-05-06 | Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/k... | Linus Torvalds | 1 | -3/+0 |
2019-05-06 | Merge branch 'core-stacktrace-for-linus' of git://git.kernel.org/pub/scm/linu... | Linus Torvalds | 1 | -2/+0 |
2019-05-06 | Merge branch 'core-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel... | Linus Torvalds | 1 | -0/+1 |
2019-04-30 | RISC-V: Implement nosmp commandline option. | Atish Patra | 1 | -1/+11 |
2019-04-30 | RISC-V: Add RISC-V specific arch_match_cpu_phys_id | Atish Patra | 2 | -2/+7 |
2019-04-30 | riscv: vdso: drop unnecessary cc-ldoption | Nick Desaulniers | 1 | -1/+1 |
2019-04-26 | riscv: call pm_power_off from machine_halt / machine_power_off | Christoph Hellwig | 1 | -6/+9 |
2019-04-26 | riscv: print the unexpected interrupt cause | Christoph Hellwig | 1 | -1/+2 |
2019-04-26 | riscv: remove duplicate macros from ptrace.h | Christoph Hellwig | 3 | -21/+12 |
2019-04-26 | riscv: remove unreachable !HAVE_FUNCTION_GRAPH_RET_ADDR_PTR code | Christoph Hellwig | 1 | -4/+0 |
2019-04-26 | riscv: cleanup the parse_dtb calling conventions | Christoph Hellwig | 2 | -4/+5 |
2019-04-26 | riscv: simplify the stack pointer setup in head.S | Christoph Hellwig | 2 | -7/+1 |
2019-04-26 | riscv: clear all pending interrupts when booting | Christoph Hellwig | 1 | -1/+2 |
2019-04-26 | riscv: remove CONFIG_RISCV_ISA_A | Christoph Hellwig | 3 | -21/+3 |
2019-04-26 | riscv: remove unreachable big endian code | Christoph Hellwig | 2 | -14/+1 |
2019-04-26 | riscv: turn mm_segment_t into a struct | Christoph Hellwig | 2 | -6/+10 |
2019-04-26 | riscv: use asm-generic/extable.h | Christoph Hellwig | 2 | -6/+2 |
2019-04-25 | riscv/signal: Fixup additional syscall restarting | Guo Ren | 1 | -0/+6 |
2019-04-14 | riscv/stacktrace: Remove the pointless ULONG_MAX marker | Thomas Gleixner | 1 | -2/+0 |
2019-04-10 | RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems | Anup Patel | 1 | -0/+8 |
2019-04-10 | Merge branch 'linus' into locking/core, to pick up fixes | Ingo Molnar | 8 | -32/+43 |
2019-04-09 | RISC-V: Add separate defconfig for 32bit systems | Anup Patel | 1 | -0/+84 |
2019-04-08 | riscv/mmiowb: Hook up mmwiob() implementation to asm-generic code | Will Deacon | 4 | -14/+17 |