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path: root/arch/riscv/mm/tlbflush.c
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2024-05-22Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-54/+21
2024-04-29riscv: mm: Always use an ASID to flush mm contextsSamuel Holland1-2/+1
2024-04-29riscv: mm: Introduce cntx2asid/cntx2version helper macrosSamuel Holland1-1/+1
2024-04-29riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Samuel Holland1-1/+1
2024-04-29riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vmaSamuel Holland1-23/+0
2024-04-29riscv: Only send remote fences when some other CPU is onlineSamuel Holland1-1/+3
2024-04-29riscv: mm: Broadcast kernel TLB flushes only when neededSamuel Holland1-13/+5
2024-04-29riscv: Use IPIs for remote cache/TLB flushes by defaultSamuel Holland1-17/+14
2024-03-26riscv: mm: Fix prototype to avoid discarding constSamuel Holland1-2/+2
2024-02-07riscv: Fix arch_tlbbatch_flush() by clearing the batch cpumaskAlexandre Ghiti1-0/+1
2024-01-31riscv: mm: execute local TLB flush after populating vmemmapVincent Chen1-1/+2
2024-01-20Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-20/+49
2024-01-11riscv: Add support for BATCHED_UNMAP_TLB_FLUSHAlexandre Ghiti1-20/+49
2023-12-14mm: Introduce flush_cache_vmap_early()Alexandre Ghiti1-0/+5
2023-11-06riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti1-10/+24
2023-11-06riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti1-56/+59
2023-11-06riscv: Improve flush_tlb_range() for hugetlb pagesAlexandre Ghiti1-1/+28
2023-11-06riscv: Improve tlb_flush()Alexandre Ghiti1-0/+7
2023-04-08RISC-V: Use IPIs for remote TLB flush when possibleAnup Patel1-15/+78
2023-03-22riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong1-1/+1
2023-03-10Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich1-11/+17
2022-12-09riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich1-17/+11
2022-01-20RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra1-7/+2
2021-07-01riscv: add ASID-based tlbflushing methodsGuo Ren1-7/+40
2021-07-01riscv: pass the mm_struct to __sbi_tlb_flush_rangeChristoph Hellwig1-9/+6
2021-05-22riscv: mm: add THP support on 64-bitNanyong Sun1-0/+7
2021-05-22riscv: mm: add param stride for __sbi_tlb_flush_rangeNanyong Sun1-5/+5
2019-10-29RISC-V: Issue a tlb page flush if possibleAtish Patra1-1/+4
2019-10-29RISC-V: Issue a local tlbflush if possible.Atish Patra1-2/+17
2019-10-29RISC-V: Do not invoke SBI call if cpumask is emptyAtish Patra1-0/+3
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig1-0/+35