Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-05-05 | RISC-V: Add bitmap reprensenting ISA features common across CPUs | Anup Patel | 1 | -0/+22 |
2019-11-12 | riscv: clean up the macro format in each header file | Zong Li | 1 | -3/+4 |
2019-06-19 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 | Thomas Gleixner | 1 | -12/+1 |
2017-09-27 | RISC-V: ELF and module implementation | Palmer Dabbelt | 1 | -0/+37 |