Age | Commit message (Expand) | Author | Files | Lines |
2024-04-26 | Merge patch series "RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE" | Palmer Dabbelt | 1 | -9/+15 |
2024-04-25 | riscv: T-Head: Test availability bit before enabling MAE errata | Christoph Müllner | 1 | -4/+10 |
2024-04-25 | riscv: thead: Rename T-Head PBMT to MAE | Christoph Müllner | 1 | -5/+5 |
2024-03-12 | riscv: errata: Rename defines for Andes | Yu Chien Peter Lin | 1 | -5/+5 |
2024-01-11 | Merge patch series "riscv: errata: thead: use riscv_nonstd_cache_ops for CMO" | Palmer Dabbelt | 1 | -2/+67 |
2024-01-10 | riscv: errata: thead: use pa based instructions for CMO | Jisheng Zhang | 1 | -12/+6 |
2024-01-10 | riscv: errata: thead: use riscv_nonstd_cache_ops for CMO | Jisheng Zhang | 1 | -2/+73 |
2023-12-06 | riscv: errata: andes: Probe for IOCP only once in boot stage | Lad Prabhakar | 1 | -7/+13 |
2023-09-27 | riscv: errata: andes: Makefile: Fix randconfig build issue | Lad Prabhakar | 1 | -0/+4 |
2023-09-08 | Merge patch series "Add non-coherent DMA support for AX45MP" | Palmer Dabbelt | 3 | -0/+68 |
2023-09-01 | riscv: errata: Add Andes alternative ports | Lad Prabhakar | 3 | -0/+68 |
2023-09-01 | RISC-V: alternative: Remove feature_probe_func | Evan Green | 1 | -8/+0 |
2023-07-06 | Merge patch series "riscv: some CMO alternative related clean up" | Palmer Dabbelt | 1 | -2/+5 |
2023-07-06 | riscv: errata: thead: only set cbom size & noncoherent during boot | Jisheng Zhang | 1 | -2/+5 |
2023-05-31 | riscv: Fix relocatable kernels with early alternatives using -fno-pie | Alexandre Ghiti | 1 | -0/+4 |
2023-04-29 | RISC-V: fix sifive and thead section mismatches in errata | Randy Dunlap | 2 | -8/+6 |
2023-04-29 | Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds | 2 | -6/+16 |
2023-04-26 | RISC-V: hwprobe: Remove __init on probe_vendor_features() | Evan Green | 1 | -3/+3 |
2023-04-19 | Merge patch series "RISC-V Hardware Probing User Interface" | Palmer Dabbelt | 1 | -0/+10 |
2023-04-19 | RISC-V: hwprobe: Support probing of misaligned access performance | Evan Green | 1 | -0/+10 |
2023-03-15 | riscv: alternatives: Rename errata_id to patch_id | Andrew Jones | 2 | -5/+5 |
2023-03-15 | riscv: alternatives: Remove unnecessary define and unused struct | Andrew Jones | 1 | -1/+1 |
2023-03-07 | RISC-V: fix taking the text_mutex twice during sifive errata patching | Conor Dooley | 1 | -1/+1 |
2023-02-22 | RISC-V: take text_mutex during alternative patching | Conor Dooley | 2 | -2/+9 |
2023-02-15 | riscv: Fix early alternative patching | Samuel Holland | 1 | -3/+1 |
2023-02-01 | riscv: switch to relative alternative entries | Jisheng Zhang | 2 | -4/+10 |
2022-10-28 | drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores | Heiko Stuebner | 1 | -0/+19 |
2022-10-13 | Merge patch series "Some style cleanups for recent extension additions" | Palmer Dabbelt | 1 | -6/+8 |
2022-10-13 | riscv: check for kernel config option in t-head memory types errata | Heiko Stuebner | 1 | -0/+3 |
2022-10-13 | riscv: use BIT() macros in t-head errata init | Heiko Stuebner | 1 | -2/+2 |
2022-10-13 | riscv: drop some idefs from CMO initialization | Heiko Stuebner | 1 | -4/+3 |
2022-09-13 | RISC-V: Clean up the Zicbom block size probing | Palmer Dabbelt | 1 | -0/+1 |
2022-08-11 | riscv: implement Zicbom-based CMO instructions + the t-head variant | Palmer Dabbelt | 1 | -0/+20 |
2022-08-07 | Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke... | Linus Torvalds | 1 | -26/+12 |
2022-08-04 | riscv: implement cache-management errata for T-Head SoCs | Heiko Stuebner | 1 | -0/+20 |
2022-07-08 | riscv: don't warn for sifive erratas in modules | Heiko Stuebner | 1 | -1/+2 |
2022-06-17 | riscv: remove usage of function-pointers from cpufeatures and t-head errata | Heiko Stuebner | 1 | -26/+12 |
2022-05-12 | riscv: add memory-type errata for T-Head | Heiko Stuebner | 4 | -1/+100 |
2022-05-12 | riscv: implement module alternatives | Heiko Stuebner | 1 | -5/+9 |
2022-05-12 | riscv: allow different stages with alternatives | Heiko Stuebner | 1 | -1/+2 |
2022-05-12 | riscv: integrate alternatives better into the main architecture | Heiko Stuebner | 2 | -76/+0 |
2022-01-09 | riscv: errata: alternative: mark vendor_patch_func __initdata | Jisheng Zhang | 1 | -1/+2 |
2021-06-02 | riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled | Vincent | 1 | -1/+1 |
2021-04-26 | riscv: sifive: Apply errata "cip-1200" patch | Vincent Chen | 1 | -0/+18 |
2021-04-26 | riscv: sifive: Apply errata "cip-453" patch | Vincent Chen | 3 | -0/+59 |
2021-04-26 | riscv: sifive: Add SiFive alternative ports | Vincent Chen | 4 | -0/+75 |
2021-04-26 | riscv: Introduce alternative mechanism to apply errata solution | Vincent Chen | 2 | -0/+70 |