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It makes no sense that some Freescale device tree files are in fsl
directory while some others not. This patch move Freescale device tree
files into fsl folder. To do that the following two steps are made:
- Move Freescale device tree files into fsl folder.
- Update the include path in these files from "fsl/*.dtsi" to "*.dtsi".
Please add "fsl/" prefix when you make dtb using Makefile.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
[scottwood: fixed cuImage rule]
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Add 1588 timer node in files:
arch/powerpc/boot/dts/bsc9131rdb.dtsi
arch/powerpc/boot/dts/bsc9132qds.dtsi
arch/powerpc/boot/dts/p1010rdb.dtsi
arch/powerpc/boot/dts/p1020rdb-pd.dts
arch/powerpc/boot/dts/p1021rdb-pc.dtsi
arch/powerpc/boot/dts/p1022ds.dtsi
arch/powerpc/boot/dts/p1025twr.dtsi
For P2020RDB-PC, registers' values should be calculated
based on default 1588 reference clock(300MHz) not 250MHz,
and fix this in file:
arch/powerpc/boot/dts/p2020rdb-pc.dtsi
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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- BSC9132 is an integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 technologies
with MAPLE-B2F baseband acceleration processing elements
- BSC9132QDS Overview
2Gbyte DDR3 (on board DDR)
32Mbyte 16bit NOR flash
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
SD slot
eTSEC1: Connected to SGMII PHY
eTSEC2: Connected to SGMII PHY
DUART interface: supports one UARTs up to 115200 bps for console display
Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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