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path: root/arch/mips/lantiq/irq.c
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2012-08-23MIPS: lantiq: external irq sources are not loaded properlyJohn Crispin1-1/+1
Support for the external interrupt unit was broken when the code was converted to devicetree support. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4231/
2012-08-23MIPS: lantiq: dont register irq_chip for the irq cascadeJohn Crispin1-0/+3
We dont want to register the irq_chip for the MIPS IRQ cascade. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4230/
2012-08-23MIPS: lantiq: timer irq can be different to 7John Crispin1-3/+16
The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq code to be able to handle this. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4229/
2012-08-23MIPS: lantiq: split up IRQ IM rangesJohn Crispin1-28/+32
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate the SVIP we need to support IM ranges that are scattered inside the register range. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4237/
2012-05-21OF: MIPS: lantiq: implement irq_domain supportJohn Crispin1-76/+102
Add support for irq_domain on lantiq socs. The conversion is straight forward as the ICU found inside the socs allows the usage of irq_domain_add_linear. Harware IRQ 0->7 are the generic MIPS IRQs. 8->199 are the Lantiq IRQ Modules. Our irq_chip callbacks need to substract 8 (MIPS_CPU_IRQ_CASCADE) from d->hwirq to find out the correct offset into the Interrupt Modules register range. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely <grant.likely@secretlab.ca> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3802/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15MIPS: lantiq: add ipi handlers to make vsmp workJohn Crispin1-0/+60
Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work on lantiq socs. The code is based on the malta implementation. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15MIPS: lantiq: enable oprofile support on lantiq targetsJohn Crispin1-0/+6
This patch sets the performance counters irq on Lantiq SoCs. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3720/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15MIPS: lantiq: clear all irqs properly on bootJohn Crispin1-5/+6
Due to missing brackets, the irq modules were not properly reset on boot. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3719/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-01-11Merge branch 'next/generic' into mips-for-linux-nextRalf Baechle1-1/+0
2011-12-08MIPS: irq: Remove IRQF_DISABLEDYong Zhang1-1/+0
Since commit [e58aa3d2: genirq: Run irq handlers with interrupts disabled], We run all interrupt handlers with interrupts disabled and we even check and yell when an interrupt handler returns with interrupts enabled (see commit [b738a50a: genirq: Warn when handler enables interrupts]). So now this flag is a NOOP and can be removed. [ralf@linux-mips.org: Fixed up conflicts in arch/mips/alchemy/common/dbdma.c, arch/mips/cavium-octeon/smp.c and arch/mips/kernel/perf_event.c.] Signed-off-by: Yong Zhang <yong.zhang0@gmail.com> To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2835/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-08MIPS: Fix up inconsistency in panic() string argument.Ralf Baechle1-6/+6
Panic() invokes printk() to add a \n internally, so panic arguments should not themselves end in \n. Panic invocations in arch/mips and elsewhere are inconsistently sometimes terminating in \n, sometimes not. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-09-21MIPS: Lantiq: Fix external interrupt sourcesJohn Crispin1-4/+2
The irq base offset needs to be ignored when matching irqs to external interrupt pins. Taking the offset into account resulted in the EIU not being brought up properly. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2616/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add initial support for Lantiq SoCsJohn Crispin1-0/+326
Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. [Ralf: Remove some cargo cult programming and fixed formatting.] Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2252/ Patchwork: https://patchwork.linux-mips.org/patch/2371/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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