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2015-04-01MIPS: Fall back to generic implementation of cmpxchg64 on 32-bit platformsDeng-Cheng Zhu1-5/+6
2015-04-01MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.hDavid Daney1-0/+74
2015-04-01MIPS: Octeon: Handle bootloader structures in little-endian mode.David Daney1-0/+55
2015-03-31MIPS, ttyFDC: Add early FDC console supportJames Hogan1-0/+11
2015-03-31MIPS: Read CPU IRQ line that FDC to routed toJames Hogan1-0/+3
2015-03-31MIPS: Add architectural FDC IRQ fieldsJames Hogan1-0/+4
2015-03-31MIPS: Add CDMM bus supportJames Hogan1-0/+87
2015-03-31MIPS: Add arch CDMM definitions and probingJames Hogan3-0/+16
2015-03-31MIPS: cevt-r4k: Move handle_perf_irq() out of headerJames Hogan1-19/+0
2015-03-31MIPS: Add support for the IMG Pistachio SoCAndrew Bresticker2-0/+39
2015-03-31MIPS: Create a common <asm/mach-generic/war.h>Kevin Cernekee22-509/+3
2015-02-22Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds47-408/+1166
2015-02-20MIPS: OCTEON: More OCTEONIII supportChandrakala Chavva2-0/+309
2015-02-20MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.Chad Reese1-20/+0
2015-02-20MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.David Daney1-3/+16
2015-02-20MIPS: OCTEON: Update octeon-model.h code for new SoCs.David Daney1-22/+85
2015-02-20MIPS: OCTEON: Implement DCache errata workaround for all CN6XXXDavid Daney1-0/+3
2015-02-20MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.hDavid Daney1-30/+105
2015-02-20MIPS: OCTEON: Implement the core-16057 workaroundDavid Daney1-0/+22
2015-02-20MIPS: OCTEON: Save and restore CP2 SHA3 stateDavid Daney1-0/+2
2015-02-20MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUsDavid Daney2-2/+15
2015-02-20MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.hDavid Daney1-6/+0
2015-02-20MIPS: ip22-gio: Remove legacy suspend/resume supportLars-Peter Clausen1-2/+0
2015-02-20mips: pci: Add ifdef around pci_proc_domainZubair Lutfullah Kakakhel1-0/+2
2015-02-20MIPS: Add set/clear CP0 macros for PageGrain registerSteven J. Hill1-0/+1
2015-02-20MIPS: Usage and cosmetic cleanups of page table bits.Steven J. Hill2-62/+38
2015-02-19Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/...Ralf Baechle29-180/+497
2015-02-19MIPS: Provide correct siginfo_t.si_stimePetr Malat2-37/+3
2015-02-18Merge tag 'for-linus-20150216' of git://git.infradead.org/linux-mtdLinus Torvalds1-2/+0
2015-02-17MIPS: kernel: elf: Improve the overall ABI and FPU mode checksMarkos Chandras1-4/+6
2015-02-17MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6Markos Chandras1-1/+2
2015-02-17MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as wellMarkos Chandras1-1/+2
2015-02-17MIPS: Make use of the ERETNC instruction on MIPS R6Markos Chandras2-4/+7
2015-02-17MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6Leonid Yegoshin2-3/+96
2015-02-17MIPS: asm: mipsregs: Add support for the LLADDR registerMarkos Chandras1-0/+2
2015-02-17MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras3-0/+5
2015-02-17MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructionsMarkos Chandras1-1/+1
2015-02-17MIPS: Emulate the new MIPS R6 BEQZC and JIC instructionsMarkos Chandras1-1/+1
2015-02-17MIPS: Emulate the new MIPS R6 BALC instructionMarkos Chandras1-1/+1
2015-02-17MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructionsMarkos Chandras1-1/+1
2015-02-17MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructionsMarkos Chandras1-1/+1
2015-02-17MIPS: Emulate the new MIPS R6 branch compact (BC) instructionMarkos Chandras1-1/+1
2015-02-17MIPS: Emulate the BC1{EQ,NE}Z FPU instructionsMarkos Chandras1-1/+2
2015-02-17MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6Markos Chandras1-0/+3
2015-02-17MIPS: kernel: r4k_switch: Add support for MIPS R6Leonid Yegoshin1-5/+7
2015-02-17MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfoMarkos Chandras1-0/+3
2015-02-17MIPS: asm: local: Set the appropriate ISA level for MIPS R6Markos Chandras1-2/+3
2015-02-17MIPS: asm: spinlock: Replace "sub" instruction with "addiu"Markos Chandras1-5/+2
2015-02-17MIPS: asm: futex: Set the appropriate ISA level for MIPS R6Markos Chandras1-4/+4
2015-02-17MIPS: asm: bitops: Update ISA constraints for MIPS R6 supportMarkos Chandras1-15/+15
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