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2012-08-31MIPS: OCTEON: Update register definitions.David Daney1-6/+101
Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
2010-10-29MIPS: Octeon: Update register definitions for CN63XX chipsDavid Daney1-13/+54
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-17MIPS: Octeon: Add hardware RNG platform device.David Daney1-0/+88
Add a platform device for the Octeon Random Number Generator (RNG). Signed-off-by: David Daney <ddaney@caviumnetworks.com> Acked-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>