kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2015-02-22	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	Linus Torvalds	1	-0/+4
2015-02-20	MIPS: Add set/clear CP0 macros for PageGrain register	Steven J. Hill	1	-0/+1
2015-02-17	MIPS: asm: mipsregs: Add support for the LLADDR register	Markos Chandras	1	-0/+2
2015-02-17	MIPS: Add LLB bit and related feature for the Config 5 CP0 register	Markos Chandras	1	-0/+1
2015-01-31	MIPS: mipsregs.h: Add write_32bit_cp1_register()	James Hogan	1	-0/+15
2014-12-12	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	Linus Torvalds	1	-0/+43
2014-11-25	MIPS: Add CP0 macros for extended EntryLo registers	Steven J. Hill	1	-0/+40
2014-11-24	MIPS: define bits introduced for hybrid FPRs	Paul Burton	1	-0/+3
2014-11-24	MIPS: cpu-probe: Set the FTLB probability bit on supported cores	Markos Chandras	1	-0/+2
2014-11-07	MIPS: Fix build with binutils 2.24.51+	Manuel Lauss	1	-1/+10
2014-08-02	MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT	Dan Carpenter	1	-1/+0
2014-08-02	MIPS: define MAAR register accessors & bits	Paul Burton	1	-0/+12
2014-08-02	MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions	Leonid Yegoshin	1	-0/+1
2014-08-02	MIPS: asm: Add register definitions for Hardware Table Walker	Markos Chandras	1	-0/+44
2014-05-30	MIPS: Add function get_ebase_cpunum	David Daney	1	-0/+9
2014-05-24	MIPS: MT: Remove SMTC support	Ralf Baechle	1	-132/+1
2014-05-23	MIPS: Disable MIPS16/microMIPS crap for platforms not supporting these ASEs.	Ralf Baechle	1	-1/+8
2014-03-27	MIPS: Add MSA register definitions & access	Paul Burton	1	-0/+1
2014-03-07	MIPS: Add CP0 CMGCRBase definitions & accessor	Paul Burton	1	-0/+6
2014-03-07	MIPS: Define Config1 cache field shifts & sizes	Paul Burton	1	-0/+12
2014-03-07	MIPS: mm: c-r4k: Detect instruction cache aliases	Markos Chandras	1	-0/+3
2014-01-23	MIPS: include linux/types.h	Qais Yousef	1	-0/+1
2014-01-22	MIPS: Add support for FTLBs	Leonid Yegoshin	1	-0/+2
2014-01-22	MIPS: Add function for flushing the TLB using the TLBINV instruction	Leonid Yegoshin	1	-0/+13
2014-01-22	MIPS: features: Add initial support for Segmentation Control registers	Steven J. Hill	1	-0/+29
2014-01-22	MIPS: Add missing bits for Config registers	Leonid Yegoshin	1	-2/+38
2013-09-19	MIPS: Add MIPS R5 config5 register.	Ralf Baechle	1	-0/+7
2013-07-01	MIPS: microMIPS: Fix improper definition of ISA exception bit.	Steven J. Hill	1	-1/+1
2013-05-09	MIPS: microMIPS: Add support for exception handling.	Steven J. Hill	1	-0/+1
2013-05-02	MIPS: microMIPS: Add instruction utility macros.	Steven J. Hill	1	-0/+18
2013-03-19	MIPS: Fix code generation for non-DSP capable CPUs	Florian Fainelli	1	-19/+190
2013-02-21	Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-j...	Ralf Baechle	1	-186/+125
2013-02-19	MIPS: Probe for and report hardware virtualization support.	David Daney	1	-0/+1
2013-02-17	MIPS: dsp: Simplify the DSP macros.	Steven J. Hill	1	-201/+30
2013-02-17	MIPS: dsp: Support toolchains without DSP ASE and microMIPS.	Steven J. Hill	1	-0/+89
2013-02-17	MIPS: dsp: Add assembler support for DSP ASEs.	Steven J. Hill	1	-17/+36
2013-02-17	MIPS: Add support for the M14KEc core.	Steven J. Hill	1	-0/+1
2013-02-01	MIPS: Whitespace cleanup.	Ralf Baechle	1	-199/+199
2013-02-01	MIPS: Whitespace cleanups and reformatting.	Steven J. Hill	1	-11/+15
2012-12-13	MIPS: PMC-Sierra Yosemite: Remove support.	Ralf Baechle	1	-8/+0
2012-12-12	MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORT	David Daney	1	-1/+1
2012-10-11	MIPS: Add detection of DSP ASE Revision 2.	Steven J. Hill	1	-0/+1
2012-10-11	MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)	Al Cooper	1	-0/+2
2012-09-28	Merge branch 'ralf-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhi...	Ralf Baechle	1	-0/+2
2012-09-14	MIPS: Add base architecture support for RI and XI.	Steven J. Hill	1	-0/+1
2012-09-14	MIPS: Add support for the 1074K core.	Steven J. Hill	1	-0/+2
2011-12-08	MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operations	Kevin Cernekee	1	-1/+8
2011-10-25	MIPS: Add accessor macros for 64-bit performance counter registers.	David Daney	1	-0/+8
2011-03-31	Fix common misspellings	Lucas De Marchi	1	-2/+2
2010-10-29	MIPS: Add BMIPS CP0 register definitions	Kevin Cernekee	1	-0/+51