Age | Commit message (Expand) | Author | Files | Lines |
2016-05-28 | MIPS: Add definitions of SegCtl registers and use them | Matt Redfearn | 1 | -3/+3 |
2015-11-11 | MIPS: Malta: Setup RAM regions via DT | Paul Burton | 1 | -0/+29 |
2014-11-24 | irqchip: mips-gic: Probe for number of external interrupts | Andrew Bresticker | 1 | -1/+0 |
2014-08-19 | MIPS: Malta: EVA: Rename 'eva_entry' to 'platform_eva_init' | Markos Chandras | 1 | -6/+16 |
2014-08-02 | MIPS: GIC: Move GIC_NUM_INTRS into platform irq.h | Jeffrey Deans | 1 | -0/+1 |
2014-05-30 | MIPS: Malta: add suspend state entry code | Paul Burton | 1 | -0/+37 |
2014-05-24 | MIPS: MT: Remove SMTC support | Ralf Baechle | 1 | -30/+0 |
2014-03-27 | MIPS: malta: Add support for SMP EVA | Markos Chandras | 1 | -0/+6 |
2014-03-27 | MIPS: malta: spaces.h: Add spaces.h file for Malta (EVA) | Markos Chandras | 1 | -0/+46 |
2014-03-27 | MIPS: malta: Configure Segment Control registers for EVA boot | Markos Chandras | 1 | -1/+108 |
2013-02-01 | MIPS: Whitespace cleanup. | Ralf Baechle | 3 | -6/+6 |
2012-12-13 | MIPS: PMC-Sierra Yosemite: Remove support. | Ralf Baechle | 1 | -1/+0 |
2011-07-25 | MIPS: Enable cpu_has_clo_clz for MIPS Technologies' platforms | Shinya Kuribayashi | 1 | -0/+2 |
2009-09-17 | MIPS: Malta: Remove pointless use use of CONFIG_CPU_HAS_LLSC | Ralf Baechle | 1 | -4/+0 |
2008-10-11 | MIPS: Move headfiles to new location below arch/mips/include | Ralf Baechle | 6 | -0/+225 |