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2022-07-05MIPS: mscc: ocelot: enable FDMA usageAlexandre Belloni1-4/+5
Enable FDMA usage by adding "fdma" resource in regs and interrupts. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-04-27MIPS: mscc: ocelot: rename pinctrl nodesMichael Walle1-2/+2
The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-08-21MIPS: mscc: ocelot: disable all switch ports by defaultVladimir Oltean1-0/+11
The ocelot switch driver used to ignore ports which do not have a phy-handle property and not probe those, but this is not quite ok since it is valid to not have a phy-handle property if there is a fixed-link. It seems that checking for a phy-handle was a proxy for the proper check which is for the status, but that doesn't make a lot of sense, since the ocelot driver already iterates using for_each_available_child_of_node which skips the disabled ports, so I have no idea. Anyway, a widespread pattern in device trees is for a SoC dtsi to disable by default all hardware, and let board dts files enable what is used. So let's do that and enable only the ports with a phy-handle in the pcb120 and pcb123 device tree files. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-30net: mscc: ocelot: add definitions for VCAP ES0 keys, actions and targetVladimir Oltean1-1/+2
As a preparation step for the offloading to ES0, let's create the infrastructure for talking with this hardware block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-30net: mscc: ocelot: add definitions for VCAP IS1 keys, actions and targetVladimir Oltean1-1/+2
As a preparation step for the offloading to IS1, let's create the infrastructure for talking with this hardware block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-14MIPS: dts: mscc: Updated changed name for miim pinctrl functionLars Povlsen1-1/+1
This is an add-on patch to the main SoC Sparx5 series (Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>). This changes the miim pinctrl function name from "miim1" to "miim" due to refactoring in the driver, obsoleting the instance number. The change in the driver was to better fit new platforms, as the instance number is redundant information. Specifically, support for the Microchip Sparx5 SoC is being submitted, where this change became necessary. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2019-08-24MIPS: dts: mscc: describe the PTP ready interruptAntoine Tenart1-2/+2
This patch adds a description of the PTP ready interrupt, which can be triggered when a PTP timestamp is available on an hardware FIFO. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: davem@davemloft.net Cc: richardcochran@gmail.com Cc: alexandre.belloni@bootlin.com Cc: UNGLinuxDriver@microchip.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: netdev@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: thomas.petazzoni@bootlin.com Cc: allan.nielsen@microchip.com
2019-08-24MIPS: dts: mscc: describe the PTP register rangeAntoine Tenart1-1/+2
This patch adds one register range within the mscc,vsc7514-switch node, to describe the PTP registers. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: davem@davemloft.net Cc: richardcochran@gmail.com Cc: alexandre.belloni@bootlin.com Cc: UNGLinuxDriver@microchip.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: netdev@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: thomas.petazzoni@bootlin.com Cc: allan.nielsen@microchip.com
2019-06-02net: mscc: ocelot: Add support for tcamHoratiu Vultur1-2/+3
Add ACL support using the TCAM. Using ACL it is possible to create rules in hardware to filter/redirect frames. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-27Merge tag 'mips_4.20' of ↵Linus Torvalds1-0/+19
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Paul Burton: - kexec support for the generic MIPS platform when running on a CPU including the MIPS Coherence Manager & related hardware. - Improvements to the definition of memory barriers used around MMIO accesses, and fixes in their use. - Switch to CONFIG_NO_BOOTMEM from Mike Rapoport, finally dropping reliance on the old bootmem code. - A number of fixes & improvements for Loongson 3 systems. - DT & config updates for the Microsemi Ocelot platform. - Workaround to enable USB power on the Netgear WNDR3400v3. - Various cleanups & fixes. * tag 'mips_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (51 commits) MIPS: Cleanup DSP ASE detection MIPS: dts: Change upper case to lower case MIPS: generic: Add Network, SPI and I2C to ocelot_defconfig MIPS: Loongson-3: Fix BRIDGE irq delivery problem MIPS: Loongson-3: Fix CPU UART irq delivery problem MIPS: Remove unused PREF, PREFE & PREFX macros MIPS: lib: Use kernel_pref & user_pref in memcpy() MIPS: Remove unused CAT macro MIPS: Add kernel_pref & user_pref helpers MIPS: Remove unused TTABLE macro MIPS: Remove unused PIC macros MIPS: Remove unused MOVN & MOVZ macros MIPS: Provide actually relaxed MMIO accessors MIPS: Enforce strong ordering for MMIO accessors MIPS: Correct `mmiowb' barrier for `wbflush' platforms MIPS: Define MMIO ordering barriers MIPS: mscc: add PCB120 to the ocelot fitImage MIPS: mscc: add DT for Ocelot PCB120 MIPS: memset: Limit excessive `noreorder' assembly mode use MIPS: memset: Fix CPU_DADDI_WORKAROUNDS `small_fixup' regression ...
2018-10-06MIPS: mscc: ocelot: add SerDes mux DT nodeQuentin Schulz1-0/+5
The Microsemi Ocelot has a set of register for SerDes/switch port muxing as well as PCIe muxing for a specific SerDes, so let's add the device and all SerDes in the Device Tree. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-06MIPS: mscc: ocelot: make HSIO registers address range a sysconQuentin Schulz1-5/+9
HSIO contains registers for PLL5 configuration, SerDes/switch port muxing and a thermal sensor, hence we can't keep it in the switch DT node. Acked-by: Paul Burton <paul.burton@mips.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-09-06MIPS: dts: mscc: Add i2c on ocelotAlexandre Belloni1-0/+19
Ocelot has an i2c controller, add it. There is only one possible pinmux configuration so add it as well. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20353/ Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com> Cc: James Hogan <jhogan@kernel.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: linux-i2c@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Allan Nielsen <allan.nielsen@microchip.com>
2018-07-31mips: dts: mscc: Add spi on OcelotAlexandre Belloni1-0/+11
Add support for the SPI controller Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20101/ Cc: Mark Brown <broonie@kernel.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-spi@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Allan Nielsen <allan.nielsen@microsemi.com>
2018-07-30MIPS: mscc: ocelot: add interrupt controller properties to GPIO controllerQuentin Schulz1-0/+3
The GPIO controller also serves as an interrupt controller for events on the GPIO it handles. An interrupt occurs whenever a GPIO line has changed. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20015/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
2018-07-26MIPS: mscc: ocelot: add MIIM1 busQuentin Schulz1-0/+16
There is an additional MIIM (MDIO) bus in this SoC so let's declare it in the dtsi. This bus requires GPIO 14 and 15 pins that need to be muxed. There is no support for internal PHY reset on this bus on the contrary of MIIM0 so there is only one register address space and not two. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20014/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
2018-07-26MIPS: mscc: ocelot: fix length of memory address space for MIIMQuentin Schulz1-1/+1
The length of memory address space for MIIM0 is from 0x7107009c to 0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in hexadecimal and not 0x36. Fixes: 49b031690abe ("MIPS: mscc: Add switch to ocelot") Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20013/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
2018-05-15MIPS: mscc: Add switch to ocelotAlexandre Belloni1-0/+88
Ocelot has an integrated switch, add support for it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: David S. Miller <davem@davemloft.net> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Signed-off-by: James Hogan <jhogan@kernel.org>
2018-03-22MIPS: mscc: Add ocelot dtsiAlexandre Belloni1-0/+117
Add a device tree include file for the Microsemi Ocelot SoC. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Allan Nielsen <Allan.Nielsen@microsemi.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/18855/ Signed-off-by: James Hogan <jhogan@kernel.org>
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