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2022-11-21Merge tag 'at91-dt-6.2-2' of ↵Arnd Bergmann1-1/+1
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt AT91 DT for 6.2 #2 It contains: - one typo fix for a SAMA7G5 pin; the pin is not used anywhere in the device trees. * tag 'at91-dt-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: sama7g5: fix signal name of pin PD8 Link: https://lore.kernel.org/r/20221118131214.301678-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21ARM: dts: uniphier: Add Pro5 board supportKunihiko Hayashi3-0/+137
Initial version of devicetree sources for Pro5 EPCORE and ProEX boards. These boards have UART, I2C, USB, eMMC and PCI endpoint in common. Pro5 EPCORE board is a kind of Pro5 reference board with PCIe endpoint card edge connector. ProEX board shares peripherals with Linux and other systems, and some of these ports are available in Linux. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221117163219.3673-3-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21ARM: dts: exynos: Add new SoC specific compatible string for Exynos3250 SoCAakarsh Jain1-1/+1
Exynos3250 and Exynos5420 are using same compatible string for MFC codec device but they have different clock hierarchy and complexity. Add new compatible string followed by mfc-v7 fallback for Exynos3250 SoC. Suggested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Aakarsh Jain <aakarsh.jain@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> Link: https://lore.kernel.org/r/20221114115024.69591-4-aakarsh.jain@samsung.com Link: https://lore.kernel.org/r/20221116093010.18515-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'imx-defconfig-6.2' of ↵Arnd Bergmann1-0/+5
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig i.MX defconfig change for 6.2: - Enable Renesas 9-series PCIe clock generator, SNVS LPGRP and i.MX8MP interconnect driver support in arm64 defconfig. - Enable Silergy SY7636A EPD PMIC, CYTTSP5 touchscreen and USB GPIO extcon support in imx_v6_v7_defconfig. * tag 'imx-defconfig-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: defconfig: Add Renesas 9-series PCIe clock generator ARM: imx_v6_v7_defconfig: Enable the cyttsp5 touchscreen ARM: imx_v6_v7_defconfig: Enable silergy,sy7636a ARM: imx_v6_v7_defconfig: Enable USB GPIO extcon support arm64: defconfig: enable i.mx 8m plus specific interconnect support arm64: defconfig: enable snvs lpgpr support Link: https://lore.kernel.org/r/20221119125733.32719-6-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21ARM: multi_v7_defconfig: enable Type-C UCSI and STM32G0 as modulesFabrice Gasnier1-0/+2
Enable the USB Type-C UCSI, and the STM32G0 UCSI drivers as modules, since used on STM32MP13 board. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Link: https://lore.kernel.org/r/20221117103931.26174-1-alexandre.torgue@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21dma-mapping: reject __GFP_COMP in dma_alloc_attrsChristoph Hellwig1-17/+0
DMA allocations can never be turned back into a page pointer, so requesting compound pages doesn't make sense and it can't even be supported at all by various backends. Reject __GFP_COMP with a warning in dma_alloc_attrs, and stop clearing the flag in the arm dma ops and dma-iommu. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
2022-11-21ARM: ixp4xx: Remove unused static mapLinus Walleij1-21/+4
The IXP4xx is just using the device tree now, only keep the static UART map if and only if we are debugging. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-20ARM: dts: nuvoton: Remove bogus unit addresses from fixed-partition nodesJonathan Neuschäfer5-10/+10
The unit addresses do not correspond to the nodes' reg properties, because they don't have any. Fixes: e42b650f828d ("ARM: dts: nuvoton: Add new device nodes to NPCM750 EVB") Fixes: ee33e2fb3d70 ("ARM: dts: nuvoton: Add Quanta GBS BMC Device Tree") Fixes: 59f5abe09f0a ("ARM: dts: nuvoton: Add Quanta GSJ BMC") Fixes: 14579c76f5ca ("ARM: dts: nuvoton: Add Fii Kudo system") Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20221031221553.163273-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: nuvoton,wpcm450-supermicro-x9sci-ln4f: Add GPIO line namesJonathan Neuschäfer1-0/+18
To make gpioinfo output more useful and enable gpiofind usage, add line names for GPIOs where the function is known. This patch follows the naming convention defined for OpenBMC, as much as possible: https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221101102916.440526-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: mtjade: Add SMPro nodesQuan Nguyen1-0/+8
Add SMPro nodes to Mt. Jade BMC. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Link: https://lore.kernel.org/r/20221118065109.2339066-1-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: mtjade,mtmitchell: Add BMC SSIF nodesQuan Nguyen2-0/+8
Add BMC SSIF node to support IPMI in-band communication. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Link: https://lore.kernel.org/r/20221024081115.3320584-1-quan@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: Add Delta AHE-50DC BMCZev Weiss2-0/+419
This is a 1U Open19 power shelf with six PSUs and 50 12VDC outputs via LM25066 efuses. It's managed by a pair of AST1250 BMCs in a redundant active/active configuration using a PCA9541 on each I2C bus to arbitrate access between the two. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20221108001551.18175-3-zev@bewilderbeest.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: rainier: Fix pca9551 nodesSantosh Puranik1-104/+104
The pca9551 compatible LED drivers are under the pca9546 mux on Rainier pass > 1. On pass 1, they are directly connected to the aspeed i2c. Signed-off-by: Santosh Puranik <santosh.puranik@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20221102223554.1738642-1-joel@jms.id.au
2022-11-20ARM: dts: aspeed: p10bmc: Add occ-hwmon nodesEddie James3-0/+70
Add the occ-hwmon nodes in order to specify that the occ-hwmon driver should not poll the OCC during initialization. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20221101213212.643472-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed-g6: Add aliases for mdio nodesPotin Lai1-0/+4
Add aliases for mdio nodes so that we can use name to lookup the bus address of Aspeed SOC. For example: root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio0 /ahb/mdio@1e650000 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio1 /ahb/mdio@1e650008 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio2 /ahb/mdio@1e650010 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio3 /ahb/mdio@1e650018 Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://lore.kernel.org/r/20221025055046.1704920-1-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: Remove MihawkJoel Stanley2-1382/+0
The platform has been removed from OpenBMC as it is unmaintained. Link: https://lore.kernel.org/r/20221020224420.635938-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: rainier,everest: Move reserved memory regionsAdriana Kobylak2-16/+17
Move the reserved regions to account for a decrease in DRAM when ECC is enabled. ECC takes 1/9th of memory. Running on HW with ECC off, u-boot prints: DRAM: already initialized, 1008 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:off) And with ECC on, u-boot prints: DRAM: already initialized, 896 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:on, ECC size:896 MiB) This implies that MCR54 is configured for ECC to be bounded at the bottom of a 16MiB VGA memory region: 1024MiB - 16MiB (VGA) = 1008MiB 1008MiB / 9 (for ECC) = 112MiB 1008MiB - 112MiB = 896MiB (available DRAM) The flash_memory region currently starts at offset 896MiB: 0xb8000000 (flash_memory offset) - 0x80000000 (base memory address) = 0x38000000 = 896MiB This is the end of the available DRAM with ECC enabled and therefore it needs to be moved. Since the flash_memory is 64MiB in size and needs to be 64MiB aligned, it can just be moved up by 64MiB and would sit right at the end of the available DRAM buffer. The ramoops region currently follows the flash_memory, but it can be moved to sit above flash_memory which would minimize the address-space fragmentation. Signed-off-by: Adriana Kobylak <anoo@us.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220916195535.1020185-1-anoo@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: Add IBM Bonnell system BMC devicetreeEddie James2-0/+912
Add a devicetree for the new Bonnell system. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Jim Wright <wrightj@linux.ibm.com> Link: https://lore.kernel.org/r/20220818202422.741275-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Enable emmc and ehci1Potin Lai1-0/+12
Enable both emmc-controller and emmc nodes for storage soultion on bletchley, and enable ehci1 node as second storage plan. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220929013130.1916525-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Update and fix gpio-line-namesPotin Lai1-2/+2
Update new GPIOM7 line name, and fixed typo of GPION6 line name New GPIO: - GPIOM7: USB_DEBUG_PWR_BTN_N Fixed GPIO: - GPION6: LED_POSTCODE_5 --> LED_POSTCODE_6 Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220929013130.1916525-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Update fusb302 nodesPotin Lai1-48/+102
1. Add interrupt pin of fusb302 on each sled. 2. Add vbus-supply property in each fusb302 node. 3. Fix BMC power-role at source and data-role at host. 4. Disable PD to avoid "HARD Reset" due to incompatible PD ver. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-5-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Bind presence-sledX pins via gpio-keysPotin Lai1-0/+35
Bind presence-sledX pins via gpio-keys driver to monitor and export GPIO pin values on DBUS using phosphor-gpio-presence service. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-4-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Disable GPIOV2 pull-downPotin Lai1-0/+10
The external pull-up cannot drive GPIOV2, so disable GPIOV2 internal pull-down resistor by the request form HW team. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Change LED sys_log_id to active lowPotin Lai1-1/+1
change LED sys_log_id to active low base on DVT schematic. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-19ARM: dts: imx6q-prti6q: Fix ref/tcxo-clock-frequency propertiesFabio Estevam1-2/+2
make dtbs_check gives the following errors: ref-clock-frequency: size (9) error for type uint32 tcxo-clock-frequency: size (9) error for type uint32 Fix it by passing the frequencies inside < > as documented in Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml. Signed-off-by: Fabio Estevam <festevam@denx.de> Fixes: 0d446a505592 ("ARM: dts: add Protonic PRTI6Q board") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19ARM: mxs: fix memory leak in mxs_machine_init()Zheng Yongjun1-1/+3
If of_property_read_string() failed, 'soc_dev_attr' should be freed before return. Otherwise there is a memory leak. Fixes: 2046338dcbc6 ("ARM: mxs: Use soc bus infrastructure") Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19ARM: dts: colibri-imx6ull: Enable dual-role switchingPhilippe Schenker1-0/+29
The Colibri standard provides a GPIO called USBC_DET to switch from USB Host to USB Device and back. Make use of this GPIO by adding it with usb-connector framework. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19ARM: kexec: make machine_crash_nonpanic_core() staticChen Lifu1-1/+1
This symbol is not used outside of the file, so mark it static. Fixes the following warning: arch/arm/kernel/machine_kexec.c:76:6: warning: symbol 'machine_crash_nonpanic_core' was not declared. Should it be static? Link: https://lkml.kernel.org/r/20220929042936.22012-5-bhe@redhat.com Signed-off-by: Chen Lifu <chenlifu@huawei.com> Signed-off-by: Baoquan He <bhe@redhat.com> Acked-by: Baoquan He <bhe@redhat.com> Cc: "Eric W . Biederman" <ebiederm@xmission.com> Cc: Petr Mladek <pmladek@suse.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Jianglei Nie <niejianglei2021@163.com> Cc: Li Chen <lchen@ambarella.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: ye xingchen <ye.xingchen@zte.com.cn> Cc: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2022-11-18arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc nodeDinh Nguyen7-0/+7
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: remove "clk-phase" in sdmmc_clkDinh Nguyen2-2/+0
Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: align mmc node names with dtschemaDinh Nguyen5-5/+5
dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18ARM: dts: lpc32xx: trim addresses to 8 digitsKrzysztof Kozlowski1-1/+1
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105049.95313-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: dts: imx: trim addresses to 8 digitsKrzysztof Kozlowski1-1/+1
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105051.95345-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18ARM: dts: omap: trim addresses to 8 digitsKrzysztof Kozlowski9-11/+11
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20221115105053.95430-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-18stackprotector: actually use get_random_canary()Jason A. Donenfeld1-8/+1
The RNG always mixes in the Linux version extremely early in boot. It also always includes a cycle counter, not only during early boot, but each and every time it is invoked prior to being fully initialized. Together, this means that the use of additional xors inside of the various stackprotector.h files is superfluous and over-complicated. Instead, we can get exactly the same thing, but better, by just calling `get_random_canary()`. Acked-by: Guo Ren <guoren@kernel.org> # for csky Acked-by: Catalin Marinas <catalin.marinas@arm.com> # for arm64 Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2022-11-18treewide: use get_random_u32_below() instead of deprecated functionJason A. Donenfeld1-1/+1
This is a simple mechanical transformation done by: @@ expression E; @@ - prandom_u32_max + get_random_u32_below (E) Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Darrick J. Wong <djwong@kernel.org> # for xfs Reviewed-by: SeongJae Park <sj@kernel.org> # for damon Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> # for infiniband Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> # for arm Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # for mmc Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2022-11-18ARM: tegra: Remove duplicate pin entry in pinmuxThierry Reding1-1/+0
For Tegra30 Pegatron Chagall, the sdmmc3_dat3_pb5 pin was defined multiple times, leading to a DT validation error. Remove the duplicate entry. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Remove unused interrupt-parent propertiesThierry Reding2-4/+0
Some boards are using the interrupt-parent property to point at the GPIO controller since it handles the interrupts for the GPIO keys. However, a node needs an interrupts property for interrupt-parent to be meaningful, which these boards don't have. gpio-keys in these cases will directly use the GPIO lines specified in the key definitions and rely on the implicit conversion of those GPIOs to interrupts by the operating system, so explicit specification of the interrupts is not required. Remove the unnecessary interrupt-parent properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fix nvidia,io-reset propertiesThierry Reding2-8/+8
Rename the unknown nvidia,ioreset property to nvidia,io-reset, as specified in the DT bindings and supported by the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Add missing power-supply for panelsThierry Reding3-0/+3
Tegra124 Nyan and Venice 2 boards were missing the required power-supply property in their display panel device tree nodes. Add these properties to fix validation errors. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fixup pinmux node namesThierry Reding9-30/+30
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Use correct compatible string for ASUS TF101 panelThierry Reding1-1/+1
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17ARM: at91: rm9200: fix usb device clock idMichael Grzeschik1-1/+1
Referring to the datasheet the index 2 is the MCKUDP. When enabled, it "Enables the automatic disable of the Master Clock of the USB Device Port when a suspend condition occurs". We fix the index to the real UDP id which "Enables the 48 MHz clock of the USB Device Port". Cc: nicolas.ferre@microchip.com Cc: ludovic.desroches@microchip.com Cc: alexandre.belloni@bootlin.com Cc: mturquette@baylibre.com Cc: sboyd@kernel.org Cc: claudiu.beznea@microchip.com Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: kernel@pengutronix.de Fixes: 02ff48e4d7f7 ("clk: at91: add at91rm9200 pmc driver") Fixes: 0e0e528d8260 ("ARM: dts: at91: rm9200: switch to new clock bindings") Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221114185923.1023249-2-m.grzeschik@pengutronix.de
2022-11-17ARM: dts: at91: sama7g5: fix signal name of pin PD8Mihai Sain1-1/+1
The signal name of pin PD8 with function D is A22_NANDCLE as it is defined in the datasheet. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> [claudiu.beznea: rebased on top of 6.1-rc1, removed fixes tag] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221114151035.2926-1-mihai.sain@microchip.com
2022-11-17ARM: dts: at91: sam9g20ek: enable udc vbus gpio pinctrlMichael Grzeschik1-0/+9
We set the PIOC to GPIO mode. This way the pin becomes an input signal will be usable by the controller. Without this change the udc on the 9g20ek does not work. Cc: nicolas.ferre@microchip.com Cc: ludovic.desroches@microchip.com Cc: alexandre.belloni@bootlin.com Cc: linux-arm-kernel@lists.infradead.org Cc: kernel@pengutronix.de Fixes: 5cb4e73575e3 ("ARM: at91: add at91sam9g20ek boards dt support") Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221114185923.1023249-3-m.grzeschik@pengutronix.de
2022-11-17ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench boardMarek Vasut1-1/+1
Replace "mdio0" node with "mdio" to match mdio.yaml DT schema. Fixes: c8ce0dd75515b ("ARM: dts: stm32: Add DHCOR based Testbench board") Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dkAmelie Delaunay1-0/+14
MCP23017 is an IO expander offering 16 input/output port expander with interrupt output. On stm32mp135f-dk, only INTA is routed (on PG12), but MCP23017 can mirror the bank B interrupts on INTA, that's why the property microchip,irq-mirror is used. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13Amelie Delaunay1-0/+7
MCP23017 interrupt line (routed on PG12) requires to be pulled-up. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-11-17Merge tag 'imx-fixes-6.1-2' of ↵Arnd Bergmann1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.1, 2nd round: - Switch to usb-role-switch for fixing USB device mode on tqma8mqml-mba8mx board, so that Dual Role is fully functional. - A series from Marek Vasut to fix dt-schema warning caused by NAND controller size-cells. - Fix file permission of imx93-pinfunc header. - Enable OCOTP clock in soc-imx8m driver to fix a kexec kernel hang issue. * tag 'imx-fixes-6.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx8m: Enable OCOTP clock before reading the register arm64: dts: imx93-pinfunc: drop execution permission arm64: dts: imx8mn: Fix NAND controller size-cells arm64: dts: imx8mm: Fix NAND controller size-cells ARM: dts: imx7: Fix NAND controller size-cells arm64: dts: imx8mm-tqma8mqml-mba8mx: Fix USB DR Link: https://lore.kernel.org/r/20221116090402.GA1274@T480 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-16ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0Andre Przywara1-0/+4
As many other Allwinner SoCs from the last years, the first USB host controller pair in the Allwinner H3 and H5 chips share a USB PHY with the MUSB OTG controller. This is probably the reason why we didn't have a "phys" property in those host controller nodes. This works fine as long as the MUSB controller driver is loaded, as this takes care of the proper PHY setup, including the muxing between MUSB and the HCI. However this requires the MUSB driver to be enabled and loaded, and also upsets U-Boot, which cannot use a HCI port without a "phys" property. Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: A64: properly connect USB PHY to port 0"), add the "phys" property to the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. This is not only the proper description of the hardware, but also avoids a nasty error message in U-Boot triggered by a recent patch. (The port never worked in host mode, but the error was suppressed due to a bug.) When using the MUSB port in OTG mode, this also fixes host mode switching, so people can use OTG adapters to connect a USB device to port 0. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221110005507.19464-1-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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