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2018-09-05ARM: dts: rockchip: add rk3188 lcd controller nodesHeiko Stuebner1-0/+82
Add the core display subsystem and vop nodes to rk3188. Vop0 has a fully dedicated set of pins and only vop1 needs to do pinctrl to have display output, so also add the necessary pinctrl entries for it. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by Sandy Huang <hjc@rock-chips.com>
2018-09-05ARM: zynq: Convert to using %pOFn instead of device_node.nameRob Herring1-1/+1
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Michal Simek <michal.simek@xilinx.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-05ARM: dts: sun8i: sun8i-r40-bananapi-m2-ultra: enable AHCICorentin Labbe1-0/+18
This patch enable the AHCI controller. Since this controller need two regulator, this patch add them. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-05ARM: dts: sun8i: r40: add sata nodeCorentin Labbe1-0/+13
R40 have a sata controller which is the same as A20. This patch adds a DT node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-05ARM: dts: meson8b: fix the clock controller register sizeMartin Blumenstingl1-1/+1
The clock controller registers are not 0x460 wide because the reset controller starts at CBUS 0x4404. This currently overlaps with the clock controller (which is at CBUS 0x4000). There is no public documentation available on the actual size of the clock controller's register area (also called "HHI"). However, in Amlogic's GPL kernel sources the last "HHI" register is HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size doesn't seem unlikely. Fixes: 4a69fcd3a10803 ("ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boards") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-05ARM: dts: meson8: fix the clock controller register sizeMartin Blumenstingl1-1/+1
The clock controller registers are not 0x460 wide because the reset controller starts at CBUS 0x4404. This currently overlaps with the clock controller (which is at CBUS 0x4000). There is no public documentation available on the actual size of the clock controller's register area (also called "HHI"). However, in Amlogic's GPL kernel sources the last "HHI" register is HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size doesn't seem unlikely. Fixes: 2c323c43a3d619 ("ARM: dts: meson8: add and use the real clock controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-04Merge tag 'socfpga_updates_for_v4.20_part1' of ↵Olof Johansson6-8/+34
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt SoCFPGA DTS updates for v4.20 - Rename de0_sockit to de0_nano_soc - Update NAND clocking - Set timer interrupt to edge sensitive - Stratix10 platform updates - Update devkit with correct i2c clock * tag 'socfpga_updates_for_v4.20_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: Rename socfpga_cyclone5_de0_{sockit,nano_soc} ARM: dts: socfpga: update NAND clocking for c5/a5 ARM: dts: arria10: update NAND clocking ARM: dts: socfpga: set timer interrupt to edge sensitive ARM: dts: socfpga: use stdout-path for chosen node arm64: dts: stratix10: i2c clock running out of spec Signed-off-by: Olof Johansson <olof@lixom.net>
2018-09-04crypto: arm/chacha20 - faster 8-bit rotations and other optimizationsEric Biggers1-134/+143
Optimize ChaCha20 NEON performance by: - Implementing the 8-bit rotations using the 'vtbl.8' instruction. - Streamlining the part that adds the original state and XORs the data. - Making some other small tweaks. On ARM Cortex-A7, these optimizations improve ChaCha20 performance from about 12.08 cycles per byte to about 11.37 -- a 5.9% improvement. There is a tradeoff involved with the 'vtbl.8' rotation method since there is at least one CPU (Cortex-A53) where it's not fastest. But it seems to be a better default; see the added comment. Overall, this patch reduces Cortex-A53 performance by less than 0.5%. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-09-04crypto: arm/ghash-ce - implement support for 4-way aggregationArd Biesheuvel3-16/+131
Speed up the GHASH algorithm based on 64-bit polynomial multiplication by adding support for 4-way aggregation. This improves throughput by ~85% on Cortex-A53, from 1.7 cycles per byte to 0.9 cycles per byte. When combined with AES into GCM, throughput improves by ~25%, from 3.8 cycles per byte to 3.0 cycles per byte. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-09-04crypto: speck - remove SpeckJason A. Donenfeld4-730/+0
These are unused, undesired, and have never actually been used by anybody. The original authors of this code have changed their mind about its inclusion. While originally proposed for disk encryption on low-end devices, the idea was discarded [1] in favor of something else before that could really get going. Therefore, this patch removes Speck. [1] https://marc.info/?l=linux-crypto-vger&m=153359499015659 Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Acked-by: Eric Biggers <ebiggers@google.com> Cc: stable@vger.kernel.org Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-09-03x86/paravirt: Use a single ops structureJuergen Gross2-4/+9
Instead of using six globally visible paravirt ops structures combine them in a single structure, keeping the original structures as sub-structures. This avoids the need to assemble struct paravirt_patch_template at runtime on the stack each time apply_paravirt() is being called (i.e. when loading a module). [ tglx: Made the struct and the initializer tabular for readability sake ] Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: xen-devel@lists.xenproject.org Cc: virtualization@lists.linux-foundation.org Cc: akataria@vmware.com Cc: rusty@rustcorp.com.au Cc: boris.ostrovsky@oracle.com Cc: hpa@zytor.com Link: https://lkml.kernel.org/r/20180828074026.820-9-jgross@suse.com
2018-09-03x86/xen: Move pv specific parts of arch/x86/xen/mmu.c to mmu_pv.cJuergen Gross1-34/+0
There are some PV specific functions in arch/x86/xen/mmu.c which can be moved to mmu_pv.c. This in turn enables to build multicalls.c dependent on CONFIG_XEN_PV. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: xen-devel@lists.xenproject.org Cc: virtualization@lists.linux-foundation.org Cc: akataria@vmware.com Cc: rusty@rustcorp.com.au Cc: hpa@zytor.com Link: https://lkml.kernel.org/r/20180828074026.820-3-jgross@suse.com
2018-09-03ARM: dts: at91: tse850: drop three indentation levelsPeter Rosin1-19/+13
Make use of the recently added &pinctrl and &watchdog labels. This makes the whole file consistent and knowledge of the ahb/apb structure is hidden. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-03ARM: dts: at91: nattis: drop three indentation levelsPeter Rosin1-42/+30
Make use of the recently added &pinctrl and &watchdog labels. This makes the whole file consistent and knowledge of the ahb/apb structure is hidden. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-03ARM: dts: imx7s: enable cpuidle driverAnson Huang2-0/+15
Enable cpuidle for i.MX7S/D using generic ARM cpuidle driver, below 2 idle states enabled: 1. ARM WFI; 2. SoC WAIT mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6sx-sdb: enable gpio buttons as wakeup sourceAnson Huang1-0/+2
This patch enables i.MX6SX SDB board's below GPIO buttons as wakeup sources: SW4(FUNC1): KEY_VOLUMEUP SW5(FUNC2): KEY_VOLUMEDOWN Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx7d-sdb: enable gpio buttons as wakeup sourceAnson Huang1-0/+2
This patch enables i.MX7D SDB board's below GPIO buttons as wakeup sources: S1(FUNC1): KEY_VOLUMEUP S3(FUNC2): KEY_VOLUMEDOWN Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx7s-warp: use SPDX-License-IdentifierPierre-Jean Texier1-38/+1
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Pierre-Jean Texier <texier.pj2@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: Add big-endian in nor node for ls1021aPrabhakar Kushwaha2-0/+4
NOR and IFC controller connectivity is big-endian. So add big-endian field in nor device tree node allowing IFC controller to read/write data from/to the flash correctly. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6ull-14x14-evk: correct machine model nameAnson Huang1-1/+1
i.MX6ULL is a lite version of i.MX6UL, its full name is i.MX6 UltraLiteLite, NOT UlltraLite. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6sll: add gpio clocksAnson Huang1-0/+6
i.MX6SLL has GPIO clock gates in CCM CCGR, add clock property for GPIO driver to make sure all GPIO banks work as expected. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6ul: Add weim nodeSébastien Szymanski1-0/+11
Add weim node for i.MX6UL SOC. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6ull: keep IMX6UL_ prefix for signals on both i.MX6UL and i.MX6ULLSébastien Szymanski1-5/+13
Signals available on both i.MX6UL and i.MX6ULL should have the same name because it is the case of all others common signals, it avoids to make mistakes (use the wrong ones) and it makes writing device tree files less complicated. For example: imx6ul-imx6ull-board.dtsi: ... pinctrl_uart5: uart5grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 >; }; imx6ul-board.dts: #include <imx6ul.dtsi> #include <imx6ul-imx6ull-board.dtsi> ... imx6ull-board.dts: #include <imx6ull.dtsi> #include <imx6ul-imx6ull-board.dtsi> ... Without this patch, the imx6ull-board.dtb will use MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX instead of MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX and the uart5 will be misconfigured. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6qdl-wandboard: Add stdout-pathTuomas Tynkkynen1-0/+4
Setting a stdout-path in the .dtb is convenient because then the user gets a serial console on the RS-232 connector without any extra effort of figuring out the relevant 'console=' boot parameter. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx7s-warp: enable i2c3 device supportPierre-Jean Texier1-0/+14
The WaRP7 has one mikroBUS socket on the back to plug click boards. This patch allows to interact with some of these i2c modules (EEPROM, RTC and so on). Signed-off-by: Pierre-Jean Texier <texier.pj2@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6Jacopo Mondi1-2/+2
The "EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation" is based on the 1.5 version of the i.Core MX6 cpu module. The 1.5 version differs from the original one for a few details, including the ethernet PHY interface clock provider. With this commit, the ethernet interface works properly: SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver While before using the 1.5 version, ethernet failed to startup do to un-clocked PHY interface: fec 2188000.ethernet eth0: could not attach to PHY Fixes: 3fe088357731 ("ARM: dts: imx6q: Add Engicam i.CoreM6 1.5 Quad/Dual MIPI starter kit support") Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6qdl: Add Engicam i.Core 1.5 MX6Jacopo Mondi1-0/+34
The 1.5 version of Engicam's i.Core MX6 CPU module features a different clock provider for the ethernet's PHY interface. Adjust the FEC ptp clock to reference CLK_ENET_REF clock source, and set SION bit of MX6QDL_PAD_GPIO_16__ENET_REF_CLK to adjust the input path of that pin. The newly introduced imx6ql-icore-1.5.dtsi allows to collect in a single place differences between version '1.0' and '1.5' of the module. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: ls1021a: Enable I2C DMA supportEsben Haabendal1-0/+6
Gives substantial performance improvement for transfers larger than 16 bytes (DMA_THRESHOLD). Smaller transfers are unaffected. Signed-off-by: Esben Haabendal <eha@deif.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: i.MX6: Use consistent node names for Engicam filesJagan Teki4-5/+5
Use consistent pinctrl node names for Engicam dt files, sufix 'grp' look consistent than actual node name - pinctrl_gpmi_nand: gpmi-nand { + pinctrl_gpmi_nand: gpminandgrp { Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6ul-isiot: Move node definitions into dtsiJagan Teki3-48/+52
Move usdhc2 and gpmi along with pinctrl nodes on imx6ul-isiot.dtsi from dts files and mark it as 'disabled' and the relevant dts will enable the status as 'okay' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx: Switch Engicam boards to use SPDX identifierJagan Teki14-446/+16
Adopt the SPDX license identifier headers to ease license compliance management. Also added Engicam Copyright on missing files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx7s: remove snvs_poweroff nodeAnson Huang1-8/+0
System poweroff is already supported by PSCI on i.MX7D, remove "snvs_poweroff" node to avoid below debug message from syscon-poweroff driver: [ 1.831414] syscon-poweroff 30370000.snvs:snvs-poweroff: pm_power_off already claimed (ptrval) psci_sys_poweroff [ 1.841707] syscon-poweroff: probe of 30370000.snvs:snvs-poweroff failed with error -16 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx7s: add i.MX7 messaging unit supportOleksij Rempel1-0/+19
Define the Messaging Unit (MU) for i.MX7 in the processor's dtsi. The respective driver is added in the next commit. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx7ulp: update pinfunc header fileAnson Huang1-1/+15
The i.MX7ULP B0 chip has some pin changes for USB and VIU module, update pinfunc header file accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx51-babbage: Add MC13892 ADC supportFabio Estevam1-0/+1
The MC13892 Analog-to-Digital input pins (ADIN5-7) are exposed on the imx51-babbage board. Pass the "fsl,mc13xxx-uses-adc" property so that the MC13892 ADC block can work. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03ARM: dts: imx6sll: add gpio-ranges propertyAnson Huang1-0/+25
Add "gpio-ranges" property to establish connections between GPIOs and PINs on i.MX6SLL pinctrl driver, for details, please refer to Documentation/devicetree/bindings/gpio/gpio.txt of "gpio-ranges" property. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-02ARM: bcm2835_defconfig: Enable bcm2835-audioStefan Wahren1-1/+1
This enables the bcm2835-audio driver, which depends on bcm2835-vchiq. After that we gain more test coverage (e.g. Kernel CI). Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
2018-09-02Merge tag 'omap-for-v4.19/fixes-v2-signed' of ↵Olof Johansson4-11/+49
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Fixes for omap variants against v4.19-rc1 These are mostly fixes related to using ti-sysc interconnect target module driver for accessing right register offsets for sgx and cpsw and for no_console_suspend regression. There is also a droid4 emmc fix where emmc may not get detected for some models, and vibrator dts mismerge fix. And we have a file permission fix for am335x-osd3358-sm-red.dts that just got added. And we must tag RTC as system-power-controller for am437x for PMIC to shut down during poweroff. * tag 'omap-for-v4.19/fixes-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap4-droid4: Fix emmc errors seen on some devices ARM: dts: Fix file permission for am335x-osd3358-sm-red.dts arm: dts: am4372: setup rtc as system-power-controller ARM: dts: omap4-droid4: fix vibrations on Droid 4 bus: ti-sysc: Fix no_console_suspend handling bus: ti-sysc: Fix module register ioremap for larger offsets ARM: OMAP2+: Fix module address for modules using mpu_rt_idx ARM: OMAP2+: Fix null hwmod for ti-sysc debug Signed-off-by: Olof Johansson <olof@lixom.net>
2018-08-31ARM: dts: pxa: add pincontrol helpersRobert Jarzmik1-0/+19
Add 3 helpers so that pincontrol definitions for pxa25x and pxa27x are easier, and can be easily converted from old mfp mach-pxa code to devicetree. An example of such conversion would be : static unsigned long mioa701_pin_config[] = { GPIO32_MMC_CLK, GPIO92_MMC_DAT_0, GPIO109_MMC_DAT_1, GPIO110_MMC_DAT_2, GPIO111_MMC_DAT_3, GPIO112_MMC_CMD, MIO_CFG_IN(GPIO78_SDIO_RO, AF0), MIO_CFG_IN(GPIO15_SDIO_INSERT, AF0), MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW), }; into: pinctrl_mmc_default: mmc-default { PMMUX(sd-insert, 15, gpio_in); PMMUX(mmclk, 32, MMCLK); PMMUX(sd-ro, 78, gpio_in); PMMUX_LPM_LOW(sd-enable, 91, gpio_out); PMMUX(mmdat0, 92, MMDAT<0>); PMMUX(mmdat1, 109, MMDAT<1>); PMMUX(mmdat2, 110, MMDAT<2>); PMMUX(mmdat3, 111, MMDAT<3>); PMMUX(mmcmd, 112, MMCMD); }; The third column of PMMUX*() helpers can be found in pincontrol muxing functions, either in pinctrl-pxa27x.c (or pinctrl-pxa25x.c), or by inspecting the pincontrol once booted in debugfs. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2018-08-31ARM: dts: BCM5301X: Specify flash partitionsRafał Miłecki5-1/+95
Most devices use Broadcom standard partitions which allows them to be described with the "brcm,bcm947xx-cfe-partitions". Exceptions are: 1) TP-LINK devices which use "os-image" partition with TRX containing kernel only + separated rootfs partition. 2) Asus RT-AC87U with custom "asus" partition. This commit also removes undocumented and unsupported linux,part-probe binding which got accidentally upstreamed while describing SPI controller. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-08-31ARM: dts: pxa: fix power i2c base addressMarcel Ziswiler1-1/+1
There is one too many zeroes in the Power I2C base address. Fix this. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2018-08-31ARM: multi_v7_defconfig: Enable VIDEO_RENESAS_FDP1Geert Uytterhoeven1-0/+1
R-Car Gen2 (and RZ/G1) SoCs have a Fine Display Processor, hence enable support for it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-31ARM: shmobile: defconfig: Enable VIDEO_RENESAS_FDP1Geert Uytterhoeven1-0/+1
R-Car Gen2 (and RZ/G1) SoCs have a Fine Display Processor, hence enable support for it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-31ARM: dts: pxa: fix the rtc controllerRobert Jarzmik2-0/+8
The RTC controller is fed by an external fixed 32kHz clock. Yet the driver wants to acquire this clock, even though it doesn't make any use of it, ie. doesn't get the rate to make calculation. Therefore, use the exported 32.768kHz clock in the PXA clock tree to make the driver happy and working. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2018-08-30ARM: multi_v7_defconfig: add Atmel I2S driverCodrin Ciubotariu1-0/+1
Add atmel-i2s driver CONFIG_SND_ATMEL_SOC_I2S. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-30ARM: configs: at91: Add I2S driver to sama5Codrin Ciubotariu1-0/+1
Add I2S CONFIG_SND_ATMEL_SOC_I2S to sama5_defconfig. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-30ARM: multi_v7_defconfig: add generic resistive touchscreenEugen Hristev1-0/+1
Add generic resistive touchscreen CONFIG_TOUCHSCREEN_ADC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-30ARM: configs: at91: add generic resistive touchscreen to sama5Eugen Hristev1-0/+1
Add generic resistive touchscreen CONFIG_TOUCHSCREEN_ADC to sama5_defconfig Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-30ARM: dts: pxa: change serial node namesRobert Jarzmik1-4/+4
Change from xxuart to serial to normalize the devicetree pxa serial support. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2018-08-30ARM: dts: exynos: Fix regulators configuration on Peach Pi/Pit ChromebooksMarek Szyprowski2-0/+6
Regulators, which are marked as 'on-in-suspend' seems to be critical for board operation, thus they must not be disabled anytime. This can be only assured by marking them as 'always-on', because otherwise some actions of their clients might result in turning them off. This patch restores suspend/resume operation on Peach-Pit Chromebook board. It partially reverts 'always-on' property removal done by the commit mentioned in the Fixes tag. Fixes: 665c441eea3d ("ARM: dts: exynos: Remove unneded always-on for regulators on Peach boards") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 19:53:42 +0300