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Configure arm64 runtime CPU speculation bug mitigations in accordance
with the 'mitigations=' cmdline option. This affects Meltdown, Spectre
v2, and Speculative Store Bypass.
The default behavior is unchanged.
Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
[will: reorder checks so KASLR implies KPTI and SSBS is affected by cmdline]
Signed-off-by: Will Deacon <will.deacon@arm.com>
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SSBS provides a relatively cheap mitigation for SSB, but it is still a
mitigation and its presence does not indicate that the CPU is unaffected
by the vulnerability.
Tweak the mitigation logic so that we report the correct string in sysfs.
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Enable CPU vulnerabilty show functions for spectre_v1, spectre_v2,
meltdown and store-bypass.
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Return status based on ssbd_state and __ssb_safe. If the
mitigation is disabled, or the firmware isn't responding then
return the expected machine state based on a whitelist of known
good cores.
Given a heterogeneous machine, the overall machine vulnerability
defaults to safe but is reset to unsafe when we miss the whitelist
and the firmware doesn't explicitly tell us the core is safe.
In order to make that work we delay transitioning to vulnerable
until we know the firmware isn't responding to avoid a case
where we miss the whitelist, but the firmware goes ahead and
reports the core is not vulnerable. If all the cores in the
machine have SSBS, then __ssb_safe will remain true.
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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__early_cpu_boot_status is of type long. Use quad
assembler directive to allocate proper size.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Arun KS <arunks@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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counters
Instead of always going via arch_counter_get_cntvct_stable to access the
counter workaround, let's have arch_timer_read_counter point to the
right method.
For that, we need to track whether any CPU in the system has a
workaround for the counter. This is done by having an atomic variable
tracking this.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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The use of a static key in a hotplug path has proved to be a real
nightmare, and makes it impossible to have scream-free lockdep
kernel.
Let's remove the static key altogether, and focus on something saner.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Let's start with the removal of the arch_timer_read_ool_enabled
static key in arch_timer_reg_read_stable. It is not a fast path,
and we can simplify things a bit.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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When a given timer is affected by an erratum and requires an
alternative implementation of set_next_event, we do a rather
complicated dance to detect and call the workaround on each
set_next_event call.
This is clearly idiotic, as we can perfectly detect whether
this CPU requires a workaround while setting up the clock event
device.
This only requires the CPU-specific detection to be done a bit
earlier, and we can then safely override the set_next_event pointer
if we have a workaround associated to that CPU.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by; Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Only arch_timer_read_counter will guarantee that workarounds are
applied. So let's use this one instead of arch_counter_get_cntvct.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Neoverse-N1 is also affected by ARM64_ERRATUM_1188873, so let's
add it to the list of affected CPUs.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[will: Update silicon-errata.txt]
Signed-off-by: Will Deacon <will.deacon@arm.com>
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New CPU, new part number. You know the drill.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Since ARM64_ERRATUM_1188873 only affects AArch32 EL0, it makes some
sense that it should depend on COMPAT.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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We currently deal with ARM64_ERRATUM_1188873 by always trapping EL0
accesses for both instruction sets. Although nothing wrong comes out
of that, people trying to squeeze the last drop of performance from
buggy HW find this over the top. Oh well.
Let's change the mitigation by flipping the counter enable bit
on return to userspace. Non-broken HW gets an extra branch on
the fast path, which is hopefully not the end of the world.
The arch timer workaround is also removed.
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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As of commit ece0e2b6406a ("mm: remove pte_*map_nested()"),
pte_unmap_nested() is no longer used and can be removed from the arm64
code.
Signed-off-by: Qian Cai <cai@lca.pw>
[will: also remove pte_offset_map_nested()]
Signed-off-by: Will Deacon <will.deacon@arm.com>
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When building with -Wunused-but-set-variable, the compiler shouts about
a number of pte_unmap() users, since this expands to an empty macro on
arm64:
| mm/gup.c: In function 'gup_pte_range':
| mm/gup.c:1727:16: warning: variable 'ptem' set but not used
| [-Wunused-but-set-variable]
| mm/gup.c: At top level:
| mm/memory.c: In function 'copy_pte_range':
| mm/memory.c:821:24: warning: variable 'orig_dst_pte' set but not used
| [-Wunused-but-set-variable]
| mm/memory.c:821:9: warning: variable 'orig_src_pte' set but not used
| [-Wunused-but-set-variable]
| mm/swap_state.c: In function 'swap_ra_info':
| mm/swap_state.c:641:15: warning: variable 'orig_pte' set but not used
| [-Wunused-but-set-variable]
| mm/madvise.c: In function 'madvise_free_pte_range':
| mm/madvise.c:318:9: warning: variable 'orig_pte' set but not used
| [-Wunused-but-set-variable]
Rewrite pte_unmap() as a static inline function, which silences the
warnings.
Signed-off-by: Qian Cai <cai@lca.pw>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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With the introduction of the config option that allows to enable kuser
helpers, it is now possible to reduce TASK_SIZE_32 when these are
disabled and 64K pages are enabled. This extends the compliance with
the section 6.5.8 of the C standard (C99).
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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When executing clock_gettime(), either in the vDSO or via a system call,
we need to ensure that the read of the counter register occurs within
the seqlock reader critical section. This ensures that updates to the
clocksource parameters (e.g. the multiplier) are consistent with the
counter value and therefore avoids the situation where time appears to
go backwards across multiple reads.
Extend the vDSO logic so that the seqlock critical section covers the
read of the counter register as well as accesses to the data page. Since
reads of the counter system registers are not ordered by memory barrier
instructions, introduce dependency ordering from the counter read to a
subsequent memory access so that the seqlock memory barriers apply to
the counter access in both the vDSO and the system call paths.
Cc: <stable@vger.kernel.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/linux-arm-kernel/alpine.DEB.2.21.1902081950260.1662@nanos.tec.linutronix.de/
Reported-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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The kvm_vcpu_pmu_{read,write}_evtype_direct functions do not handle
the cycle counter use-case, this leads to inaccurate counts and a
WARN message when using perf with the cycle counter (-e cycle).
Let's fix this by adding a use case for pmccfiltr_el0.
Fixes: 39e3406a090a ("arm64: KVM: Avoid isb's by using direct pmxevtyper sysreg")
Reported-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain into arm/dt
Bitmain SoC changes for v5.2:
- Added GPIO support for BM1880 SoC based on Designware APB GPIO
controller
- Added GPIO line names for Sophon Edge board based on 96Boards CE
specification for accessing GPIOs using line names from userspace
tools like MRAA.
- Added pinctrl node for BM1880 SoC as a child node of sctrl syscon
node.
- Added pinctrl support to UARTs exposed on the Sophon Edge board.
* tag 'bitmain-soc-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain:
arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge
arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board
arm64: dts: bitmain: Add GPIO support for BM1880 SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
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arm/defconfig
mvebu arm64 for 5.2 (part 1)
- Update the defconfig to enable the mv-xor driver found on the
Armada 3700
* tag 'mvebu-arm64-5.2-1' of git://git.infradead.org/linux-mvebu:
arm64: defconfig: enable mv-xor driver
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree update for 5.2:
- Add initial i.MX8MM SoC and EVK board support.
- Enable OPP table for cpufreq support on i.MX8MQ, i.MX8QXP and
i.MX8MM.
- A series from Andrey Smirnov to enable PCIe support for i.MX8MQ.
- Add TMU (Thermal Management Unit) device on i.MX8MQ for managing
thermal of CPU, GPU, and VPU.
- Add SDMA and SAI2 devices for i.MX8MQ SoC and enable wm8524 audio
support on EVK board.
- Add LPUART, OCOTP and GPU devices for i.MX8MQ SoC.
- Add initial i.MX8MQ based Zii Ultra board support
- Add SCU general IRQ and watchdog support for i.MX8QXP.
- Add audio related devices and PMU for LS1028A.
- Enable SATA and cpuidle support for LX2160A.
- Other small random updates.
* tag 'imx-dt64-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits)
arm64: dts: lx2160a: add cpu idle support
arm64: dts: imx8mq: fix GPU clock frequency
arm64: dts: fsl: imx8mq-evk: link regulator to GPU domain
arm64: dts: imx8mm: Add cpufreq properties
arm64: dts: imx8qxp-mek: Add i2c1 with pca9646
arm64: dts: imx8qxp: enable scu general irq channel
arm64: dts: imx8mq: add GPU node
arm64: dts: imx: add Zii Ultra board support
arm64: dts: imx8mq: fix higher CPU operating point
arm64: dts: imx8mq-evk: Enable PCIE0 interface
arm64: dts: imx8mq: Add nodes for PCIe IP blocks
arm64: dts: imx8mq: Combine PCIE power domains
arm64: dts: imx8mq: Add a node for SRC IP block
arm64: dts: imx8mq: Mark iomuxc_gpr as i.MX6Q compatible
arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes
arm64: dts: lx2160a: add sata node support
arm64: dts: ls1028a: Corrected the SATA ecc address
arm64: dts: imx8mq: Change ahb clock for imx8mq
arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
arm64: dts: imx8qxp: add system controller watchdog support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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The file offset argument to the arm64 sys_mmap() implementation is
scaled from bytes to pages by shifting right by PAGE_SHIFT.
Unfortunately, the offset is passed in as a signed 'off_t' type and
therefore large offsets (i.e. with the top bit set) are incorrectly
sign-extended by the shift. This has been observed to cause false mmap()
failures when mapping GPU doorbells on an arm64 server part.
Change the type of the file offset argument to sys_mmap() from 'off_t'
to 'unsigned long' so that the shifting scales the value as expected.
Cc: <stable@vger.kernel.org>
Signed-off-by: Boyang Zhou <zhouby_cn@126.com>
[will: rewrote commit message]
Signed-off-by: Will Deacon <will.deacon@arm.com>
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The nature of silicon errata means that the Kconfig help text for our
various software workarounds has been written by many different people.
Along the way, we've accumulated typos and inconsistencies which make
the options needlessly difficult to read.
Fix up minor issues with the help text.
Signed-off-by: Will Deacon <will.deacon@arm.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/defconfig
Renesas ARM64 Based SoC Defconfig Updates for v5.2
+ Enable support for RX-8571/RX-8581 RTC
* tag 'renesas-arm64-defconfig-for-v5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: defconfig: enable RX-8581 config option
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/defconfig
Allwinner arm64 defconfig changes for 5.2
Just a single patch to enable our SPI controller on the arm64 defconfig.
* tag 'sunxi-config64-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: defconfig: Enable SPI_SUN6I
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/defconfig
arm64: tegra: Default configuration updates for v5.2-rc1
These patches enable PWM fan and Tegra HDA support in the 64-bit ARM
default configuration, so that these features are enabled by default.
* tag 'tegra-for-5.2-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Add PWM Fan support
arm64: defconfig: Enable Tegra HDA support
Signed-off-by: Olof Johansson <olof@lixom.net>
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Commit 7ee7ef24d02d ("scsi: arm64: defconfig: enable configs for Hisilicon ufs")
set 'CONFIG_SCSI_UFS_HISI=y', but the configs it depends
on
(CONFIG_SCSI_HFSHCD_PLATFORM && CONFIG_SCSI_UFSHCD)
were left to being built as modules.
Commit 1f4fa50dd48f ("arm64: defconfig: Regenerate for v4.20") "fixed"
that by reverting to 'CONFIG_SCSI_UFS_HISI=m'.
Thing is, if the rootfs is stored in the on-board flash (which
is the "canonical" way of doing things), we either need these drivers
to be built-in, or we need to fiddle with an initramfs to access that
flash and eventually load the modules installed over there.
The former is the easiest, do that.
Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/defconfig
ARM64 defconfig updates for v5.1
- 'make savedefconfig' cleanup
- Enable PCIE_ALTERA and PCIE_ALTERA_MSI
- Enable the Intel Stratix10 Service layer driver, FPGA manager and
Altera Freeze Bridge driver.
- Adds the Intel Agilex platform to the arm64 defconfig
* tag 'arm64_defconfig_for_v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: defconfig: include the Agilex platform to the arm64 defconfig
arm64: defconfig: enable fpga and service layer
arm64: defconfig: enable PCIE_ALTERA
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add pinctrl support for UARTs exposed on the Sophon Edge board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports
pinmuxing and the pinctrl registers are part of the sctrl block.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Add GPIO line names for Sophon Edge board based on BM1880 SoC from
Bitmain. Line names are based on the board schematics as well as the
96Boards Consumer Edition specification v1.0.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
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Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
controller IP. IP exposes 3 GPIO controllers with a total of 72 pins.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes
Allwinner fixes for 5.1
- Pinctrl related fixes for the A33 NAND controller
- Fix the refcounting of DT nodes in our core code
- Fix for a typo'd DT property
* tag 'sunxi-fixes-for-5.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun8i: a33: Reintroduce default pinctrl muxing
arm64: dts: allwinner: a64: Rename hpvcc-supply to cpvdd-supply
ARM: sunxi: fix a leaked reference by adding missing of_node_put
ARM: sunxi: fix a leaked reference by adding missing of_node_put
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.2, second round
DTC warning fixes: move fixed-clocks, timer and pmu nodes outside of soc
node.
* tag 'samsung-dt64-5.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Move fixed-clocks out of soc
arm64: dts: exynos: Move pmu and timer nodes out of soc
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt
Qualcomm ARM64 Updates for v5.2 - Part 2
* Add ADC temp for temp alarm node on PM8998
* Add ref clks for DSI PHYs on SDM845 and MSM8916
* Add CPU capacity and topology on SDM845
* Add display and gpu related nodes on MSM8996
* Add sound and hdmi display support on DB820C
* Fixup thermal nodes on MSM8998 platform
* tag 'qcom-arm64-for-5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20
arm64: dts: msm8998: thermal: Fix number of supported sensors
arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones
arm64: dts: db820c: Add sound card support
arm64: dts: apq8096-db820c: Add HDMI display support
arm64: dts: Add Adreno GPU definitions
arm64: qcom: msm8996.dtsi: Add Display nodes
arm64: dts: msm8996: Add display smmu node
arm64: dts: msm8996: Add graphics smmu node
arm64: dts: sdm845: Add CPU capacity values
arm64: dts: sdm845: Add CPU topology
arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs
arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY
arm64: dts: qcom: pm8998: Use ADC temperature to temp-alarm node
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Bulk conversion of remaining gpios to the helper constants, new peripherals
for the rk3328-roc-cc and some minor fixes for rk3399 and rockpro64.
* tag 'v5.2-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64
arm64: dts: rockchip: fix cts, rts pin assign of UART3 for rk3399
arm64: dts: rockchip: bulk convert gpios to their constant counterparts
arm64: dts: rockchip: enable display nodes on rk3328-roc-cc
arm64: dts: rockchip: eMMC additions for rk3328-roc-cc
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
mt8173:
- use assinged-clocks and assigned-clock-parents
- fix compatible for SoC to a72
- add pmu nodes
mt8183:
- add sysirq binding
- add pinctrl dt header file
mt7629:
- update bindings description fo sysirq, uart and scpsys
mt8516:
- add binding description for watchdog, timer, uart and sysirq
* tag 'v5.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm64: dts: mt8173: add pmu nodes for mt8173
arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72
dt-bindings: irq: mtk,sysirq: add support for MT8516
dt-bindings: serial: mtk-uart: add support for MT8516
dt-bindings: timer: mtk-timer: add support for MT8516
dt-bindings: wdog: mtk-wdt: add support for MT851
dt-bindings: soc: fix a typo for MT7623A
dt-bindings: mediatek: update bindings for MT7629 SoC
arm64: dts: mt8183: add pinctrl file
dt-bindings: mtk-sysirq: Add compatible for Mediatek MT8183
arm64: dts: Using standard CCF interface to set vcodec clk
Signed-off-by: Olof Johansson <olof@lixom.net>
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The old "cooling-{min,max}-state" properties for thermal bindings were
ratified to "cooling-{min,max}-level" by commit eb168b70dea5 ("of:
thermal: Fix inconsitency between cooling-*-state and cooling-*-level"),
which were later removed entirely by commit e04907dbc259 ("dt-bindings:
thermal: Remove "cooling-{min|max}-level" properties").
The pwm-fan binding, however, was apparently in-flight in parallel with
that ratification, and so managed to introduce an example of the old
properties which escaped the scope of the later cleanup and has thus
continued to be dutifully copied for new boards despite being useless.
Clean up these remaining undocumented anachronisms to minimise any
further confusion.
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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mvebu dt64 for 5.2 (part 1)
Add wlan_disable signal hog for rfkill signal on clearfog-gt-8k
(Armada 8040 based board)
* tag 'mvebu-dt64-5.2-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: clearfog-gt-8k: add wlan_disable signal hog
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt
Qualcomm ARM64 Updates for v5.2
* Add gpio ranges for Qualcomm platforms
* Fix MSM8998 BLSP2 I2C5 address
* Add MSM8998 UFS nodes and associated information
* Add SDM845 interconnect header and usage
* Add ADSP and CDSP PAS, RMTFS memory, and UFS phy reset on SDM845
* Update reserved memory map on SDM845
* Add QCS404 spmi regulators, ethernet, bluetooth, and uart3
* Remove remotely-controlled property as default for BAM on QCS404
* Add spmi regulators on PMS405
* Fixup QCS404 l3 voltages and regulator supply names
* Fixup thermal trip names on Qualcomm platforms
* Add thermal sensors on Qualcomm platforms
* Remove invalid efficiency property on MSM8998
* Change QCS404-evb compatible to help distinguish platforms
* Add rpmhd header file and convert to use definitions on SDM845
* Add interconnect header file on SDM845
* Add PMS405 ADC binding
* tag 'qcom-arm64-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (38 commits)
arm64: dts: sdm845: Introduce ADSP and CDSP PAS nodes
arm64: dts: qcom: sdm845: Define rmtfs memory
arm64: dts: qcom: sdm845: Update reserved memory map
arm64: dts: sdm845: Add UFS PHY reset
arm64: dts: qcom: msm8998: Fix blsp2_i2c5 address
arm64: dts: qcom: qcs404-evb: Change the compatible to distinguish platforms
arm64: dts: qcom: pmi8998: add gpio-ranges
arm64: dts: qcom: pmi8994: add gpio-ranges
arm64: dts: qcom: pm8998: add gpio-ranges
arm64: dts: qcom: pm8005: add gpio-ranges
arm64: dts: msm8998: Add UFS phy reset
arm64: dts: msm8916: thermal: Convert camera trip type to hot
arm64: dts: msm8996: thermal: Make trip names consistent
arm64: dts: msm8916: thermal: Make trip names consistent
arm64: dts: msm8998: thermal: Make trip names consistent
arm64: dts: sdm845: thermal: Add temperature sensors near major peripherals
arm64: dts: msm8998: thermal: Add temperature sensors near major peripherals
arm64: dts: msm8998: thermal: GPU has two sensors, add the second
arm64: dts: msm8998: thermal: Fix the gpu sensor number
arm64: dts: msm8998: thermal: Fix the cpu sensor numbers
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt
arm64: dts: Amlogic updates for v5.2, round 2
- add display/gfx support for G12a boards
- enable USB for g12a boards
* tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (26 commits)
arm64: dts: meson-g12a-u200: Add support for Video Display
arm64: dts: meson-g12a-sei510: Add support for Video Display
arm64: dts: meson-g12a-x96-max: Add support for Video Display
arm64: dts: meson-g12a: Add AO-CEC nodes
arm64: dts: meson-g12a: Add VPU and HDMI related nodes
arm64: dts: meson-g12a-x96-max: Enable USB
arm64: dts: meson-g12a-u200: Enable USB
arm64: dts: meson-g12a-sei510: Enable USB
arm64: dts: meson-g12a-sei510: Add ADC Key and BT support
arm64: dts: meson-g12a-u200: add regulators
arm64: dts: meson: g12a: Add mali-g31 gpu node
arm64: dts: meson: g12a: Add G12A USB nodes
arm64: dts: meson: g12a: Add SAR ADC node
dt-bindings: power: amlogic, meson-gx-pwrc: Add G12A compatible
arm64: dts: meson-gxm: Add Mali-T820 node
dt-bindings: gpu: mali-midgard: Add resets property
dt-bindings: clock: meson8b: export the video decoder clocks
dt-bindings: clock: meson8b: export the VPU clock
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
dt-bindings: clock: meson8b: drop the "ABP" clock definition
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt
Second Round of Renesas ARM64 Based SoC DT Updates for v5.2
* R-Car H3 (r8a7795), M3-N (r8a77965) and E3 (r8a77990) SoCs
- Describe CMT devices in DT
* R-Car M3-N (r8a77965) SoC
- Remove unecessary reg-names of display node
* R-Car V3H (r8a77980) SoC
- Add missing "renesas,id" property to VIN of device tree
* RZ/G2E (r8a774c0) based CAT874 board
- Add USB-HOST support
* tag 'renesas-arm64-dt2-for-v5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: renesas: r8a77980: Add "renesas,id" to VIN
arm64: dts: renesas: r8a77965: Remove reg-names of display node
arm64: dts: renesas: r8a77990: Add CMT device nodes
arm64: dts: renesas: r8a77965: Add CMT device nodes
arm64: dts: renesas: r8a7795: Add CMT device nodes
arm64: dts: renesas: cat874: Add USB-HOST support
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner H3/H5 changes for 5.2
Our usual bunch of changes shared between arm and arm64, the most notable
one being:
- Fix of improper usage of DT bindings, thanks to the DT validation
- Add the SID for the H3 and H5
- New board: RerVision H3-DVK
* tag 'sunxi-h3-h5-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun8i: mapleboard: Remove cd-inverted
ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI
ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board
ARM: dts: sun8i: h3: Add default dr_mode
ARM: dts: sun8i: h3: Refactor the pinctrl node names
ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry
ARM: dts: sunxi: h3/h5: Add device node for SID
ARM: dts: sun8i-h3: Add support for the RerVision H3-DVK board
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner arm64 DT changes for 5.2
Our usual bunch of patches, the most notable one being:
- Fixing the DTC warnings
- Fix DT bindings not being properly respected, thanks to the DT
validation
- New Board: Oceanic 5205, Beelink GS1, Orange Pi3
* tag 'sunxi-dt64-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (22 commits)
arm64: dts: allwinner: a64-amarula-relic: Add OV5640 camera node
arm64: dts: allwinner: a64: Add pinmux setting for CSI MCLK on PE1
arm64: dts: allwinner: Fix DE2 bus node name
arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI
arm64: dts: allwinner: h6: Add MMC1 pins
arm64: dts: allwinner: h6: Add Orange Pi 3 DTS
arm64: dts: allwinner: h6: Introduce Beelink GS1 board
dt-bindings: vendor-prefixes: add AZW
arm64: dts: allwinner: h6: move MMC pinctrl to dtsi
arm64: dts: allwinner: h6: Add device node for SID
arm64: dts: allwinner: a64: Fix the Codec I2S binding
arm64: dts: allwinner: a64: Add default dr_mode
arm64: dts: allwinner: Fix pinctrl node names
arm64: dts: allwinner: a64: Add missing PIO clocks
arm64: dts: allwinner: a64: Fix display pipeline endpoints
arm64: dts: allwinner: a64: Fix the TCON output clock
arm64: dts: allwinner: h6: Add Video Engine node
arm64: dts: allwinner: a64: Add cross links for the mixers
arm64: allwinner: a64: Add Oceanic 5205 5inMFD initial support
dt-bindings: Add vendor prefix for oceanic
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner DT changes for 5.2
This PR is pretty significant, but it been mostly about:
- Fixing the DTC warnings in most of our DT. We're now down to 2
warnings, from several thousands.
- Fixing a good number of minor issues, typos, and so on thanks to the DT
validation tools
- Describe the MBUS controller and the special DMA RAM mapping on the A13
- Add support for the LRADC on the A83t
- Add support for the I2C bus used for the PMIC on the A33
- Start using the DT annotation /omit-if-no-ref/ on our pinctrl nodes
* tag 'sunxi-dt-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (65 commits)
ARM: dts: sun8i: a83t: Enable USB OTG controller on some boards
ARM: dtsi: axp81x: add USB power supply node
ARM: dts: sun5i: Reorder pinctrl nodes
ARM: dts: sun6i: i7: Remove useless property
ARM: dts: sun4i: lime: Fix the USB PHY ID detect GPIO properties
ARM: dts: sun4i: protab2: Remove stale pinctrl-names entry
ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI
ARM: dts: sun8i: v40: bananapi-m2-berry: Sort device node dereferences.
ARM: dts: sun5i: Add the MBUS controller
dt-bindings: sunxi: Add compatible for OrangePi 3 board
ARM: dts: sun8i: a83t: Add I2C2 pinmux setting for PE pins
dt-bindings: arm: sunxi: Add Beelink GS1 board
ARM: dts: sun8i: tbs-a711: Add support for volume keys input
ARM: dts: sunxi: Add R_LRADC support for A83T
ARM: dts: sunxi: Improve A33 NAND transfers by using DMA
ARM: dts: sun8i: tbs-a711: Enable UART2 (for NEO-6M GPS module)
ARM: dts: sunxi: Remove useless pinctrl nodes
ARM: dts: sunxi: Remove pinctrl groups setting bias
ARM: dts: sunxi: Remove useless address and size cells
ARM: dts: sunxi: Conform to DT spec for NAND controller
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.2-rc1
This contains a bunch of changes all across the board. Perhaps the most
notable introduction here is support for the Jetson Nano Developer Kit.
* tag 'tegra-for-5.2-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Remove regulator hacks on Jetson TX2
arm64: tegra: Enable XUSB on P2771
arm64: tegra: Add XUSB and pad controller on Tegra186
arm64: tegra: Add NVIDIA Jetson Nano Developer Kit support
arm64: tegra: smaug: Move PLL power supplies to XUSB pad controller
arm64: tegra: jetson-tx1: Move PLL power supplies to XUSB pad controller
arm64: tegra: Enable command queue for Tegra186 SDMMC4
arm64: tegra: Fix default tap and trim values
arm64: tegra: Add supply for temperature sensor on P2888
arm64: tegra: Enable aconnect, ADMA and AGIC on Jetson TX1
arm64: tegra: Add L2 cache topology to Tegra210
arm64: tegra: Enable CPU idle support for Shield
arm64: tegra: Enable CPU idle support for Smaug
arm64: tegra: Enable CPU idle support for Jetson TX1
arm64: tegra: Add CPU idle states properties for Tegra210
arm64: tegra: Fix timer node for Tegra210
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.2
- Add base support for Agilex platform
- Add 'cap-mmc-highspeed' Stratix10 and 32-bit SoCFPGA platform
- Increase Stratix10 QSPI support to 100 MHz
* tag 'socfpga_dts_updates_for_v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: agilex: Add initial support for Intel's Agilex SoCFPGA
arm64: dts: stratix10: increase QSPI max frequency to 100MHz
arm64: dts: stratix10: enable MMC highspeed support
ARM: dts: socfpga: enable MMC highspeed support
Signed-off-by: Olof Johansson <olof@lixom.net>
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into arm/dt
ARM64: DT: Hisilicon SoCs DT updates for 5.2
* Hi3660 SoC and related boards:
- Added DMA support for the uart nodes
- Added the asp DMA controller node
- Replaced dma-min-chan with dma-channel-mask to follow the binding
* Hi3670 SoC and related boards:
- Reused Hi3660 reset to support Hi3670, updated the binding
document and added dts node
- Reused Hi3660 MMC controller to support Hi3670, updated the
binding document and added related nodes to support SD and WiFi
for the SoC and hikey970 board
- Added UFS controller node
* tag 'hisi-arm64-dt-for-5.2' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisilicon: hi3670: Add UFS controller support
arm64: dts: hi3660: Fixup unofficial dma-min-chan to dma-channel-mask
arm64: dts: hi3660: Add hisi asp dma device
arm64: dts: hi3660: Add dma to uart nodes
arm64: dts: hisilicon: hikey970: Add SD and WiFi support
arm64: dts: hisilicon: hi3670: Add MMC controller support
dt-bindings: mmc: Add HI3670 MMC controller binding
arm64: dts: hisilicon: hi3670: Add reset controller support
dt-bindings: reset: Add HI3670 reset controller binding
Signed-off-by: Olof Johansson <olof@lixom.net>
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arm/dt
arm64: dts: zynqmp: DT changes for v5.2
- Align xlnx-zynqmp-clk.h file name and separate
binding for clock driver
- Add TI quirks to zynqmp boards
* tag 'zynqmp-dt-for-v5.2' of https://github.com/Xilinx/linux-xlnx:
arm64: zynqmp: dt: Add TI PHY quirk
dt-bindings: xilinx: Separate clock binding from firmware doc
include: dt-binding: clock: Rename zynqmp header file
Signed-off-by: Olof Johansson <olof@lixom.net>
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