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path: root/arch/arm64/include/asm/fpsimd.h
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2021-12-14arm64/sve: Generalise vector length configuration prctl() for SMEMark Brown1-3/+3
2021-10-26arm64/sve: Add stub for sve_max_virtualisable_vl()Mark Brown1-0/+5
2021-10-21arm64/sve: Explicitly load vector length when restoring SVE stateMark Brown1-1/+1
2021-10-21arm64/sve: Put system wide vector length information into structsMark Brown1-15/+86
2021-10-21arm64/sve: Use accessor functions for vector lengths in thread_structMark Brown1-1/+1
2021-10-21arm64/sve: Make access to FFR optionalMark Brown1-3/+3
2021-10-21arm64/sve: Make sve_state_size() staticMark Brown1-2/+0
2021-10-21arm64/sve: Remove sve_load_from_fpsimd_state()Mark Brown1-2/+0
2021-08-02arm64/sve: Make fpsimd_bind_task_to_cpu() staticMark Brown1-1/+0
2021-05-26arm64/sve: Skip flushing Z registers with 128 bit vectorsMark Brown1-1/+1
2021-05-01Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+11
2021-04-08arm64/sve: Rework SVE access trap to convert state in registersMark Brown1-0/+1
2021-03-31arm64: sve: Provide sve_cond_update_zcr_vq fallback when !ARM64_SVEXiaofei Tan1-0/+2
2021-03-18arm64: sve: Provide a conditional update accessor for ZCR_ELxMarc Zyngier1-0/+9
2020-09-21arm64/sve: Implement a helper to load SVE registers from FPSIMD stateJulien Grall1-0/+2
2020-09-21arm64/sve: Implement a helper to flush SVE registersJulien Grall1-0/+1
2019-08-05arm64: remove pointless __KERNEL__ guardsMark Rutland1-1/+1
2019-07-08Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-4/+1
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
2019-06-04arm64/fpsimd: Introduce fpsimd_save_and_flush_cpu_state() and use itJulien Grall1-3/+1
2019-06-04arm64/fpsimd: Remove the prototype for sve_flush_cpu_state()Julien Grall1-1/+0
2019-04-18arm64/sve: Clarify vq map semanticsDave Martin1-4/+0
2019-03-29arm64/sve: In-kernel vector length availability query interfaceDave Martin1-0/+29
2019-03-29arm64/sve: Enable SVE state tracking for non-task contextsDave Martin1-1/+2
2019-03-29arm64/sve: Check SVE virtualisabilityDave Martin1-0/+1
2018-07-12arm64: move sve_user_{enable,disable} to <asm/fpsimd.h>Mark Rutland1-1/+16
2018-05-25arm64/sve: Move sve_pffr() to fpsimd.h and make inlineDave Martin1-0/+13
2018-05-25arm64/sve: Move read_zcr_features() out of cpufeature.hDave Martin1-0/+2
2018-05-25KVM: arm64: Optimise FPSIMD handling to reduce guest/host thrashingDave Martin1-0/+6
2018-03-28arm64: fpsimd: Split cpu field out from struct fpsimd_stateDave Martin1-27/+2
2018-03-27arm64: fpsimd: include <linux/init.h> in fpsimd.hWill Deacon1-0/+1
2018-03-26arm64: capabilities: Update prototype for enable call backDave Martin1-1/+3
2018-01-16arm64: fpsimd: Fix state leakage when migrating after sigreturnDave Martin1-1/+1
2017-11-03arm64/sve: KVM: Prevent guests from using SVEDave Martin1-0/+1
2017-11-03arm64/sve: Add prctl controls for userspace vector length managementDave Martin1-0/+14
2017-11-03arm64/sve: ptrace and ELF coredump supportDave Martin1-1/+11
2017-11-03arm64/sve: Probe SVE capabilities and usable vector lengthsDave Martin1-0/+14
2017-11-03arm64/sve: Backend logic for setting the vector lengthDave Martin1-0/+8
2017-11-03arm64/sve: Signal handling supportDave Martin1-0/+1
2017-11-03arm64/sve: Core task context handlingDave Martin1-0/+16
2017-11-03arm64/sve: Low-level SVE architectural state manipulation functionsDave Martin1-0/+5
2017-08-04arm64: neon: Remove support for nested or hardirq kernel-mode NEONDave Martin1-14/+0
2017-08-04arm64: neon: Allow EFI runtime services to use FPSIMD in irq contextDave Martin1-0/+4
2014-05-08arm64: add support for kernel mode NEON in interrupt contextArd Biesheuvel1-0/+15
2014-05-08arm64: defer reloading a task's FPSIMD state to userland resumeArd Biesheuvel1-0/+5
2014-05-08arm64: add abstractions for FPSIMD state manipulationArd Biesheuvel1-0/+3
2012-11-08arm64: elf: fix core dumping definitions for GP and FP registersWill Deacon1-3/+2
2012-09-17arm64: Floating point and SIMDCatalin Marinas1-0/+64