| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-07-12 | Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)" | Will Deacon | 1 | -1/+1 |
| 2021-06-01 | arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) | Will Deacon | 1 | -1/+1 |
| 2021-02-26 | arm64: kasan: simplify and inline MTE functions | Andrey Konovalov | 1 | -1/+0 |
| 2020-12-22 | arm64: kasan: align allocations for HW_TAGS | Andrey Konovalov | 1 | -0/+3 |
| 2020-10-28 | arm64: avoid -Woverride-init warning | Arnd Bergmann | 1 | -0/+1 |
| 2020-10-26 | treewide: Convert macro and uses of __section(foo) to __section("foo") | Joe Perches | 1 | -1/+1 |
| 2020-02-22 | arm64: Ask the compiler to __always_inline functions used by KVM at HYP | James Morse | 1 | -1/+1 |
| 2019-10-25 | arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419 | James Morse | 1 | -1/+2 |
| 2019-08-13 | arm64: prefer __section from compiler_attributes.h | Nick Desaulniers | 1 | -1/+1 |
| 2019-07-08 | Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a... | Linus Torvalds | 1 | -1/+4 |
| 2019-06-19 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 | Thomas Gleixner | 1 | -12/+1 |
| 2019-06-17 | arm64/mm: Correct the cache line size warning with non coherent device | Masayoshi Mizuma | 1 | -0/+7 |
| 2019-06-04 | arm64: cacheinfo: Update cache_line_size detected from DT or PPTT | Shaokun Zhang | 1 | -5/+1 |
| 2019-01-16 | kasan, arm64: remove redundant ARCH_SLAB_MINALIGN define | Andrey Konovalov | 1 | -2/+0 |
| 2019-01-09 | kasan, arm64: use ARCH_SLAB_MINALIGN instead of manual aligning | Andrey Konovalov | 1 | -0/+6 |
| 2018-10-16 | arm64: cpufeature: Fix handling of CTR_EL0.IDC field | Suzuki K Poulose | 1 | -0/+40 |
| 2018-07-05 | arm64: Fix mismatched cache line size detection | Suzuki K Poulose | 1 | -0/+4 |
| 2018-05-15 | arm64: Increase ARCH_DMA_MINALIGN to 128 | Catalin Marinas | 1 | -2/+2 |
| 2018-05-11 | Revert "arm64: Increase the max granular size" | Catalin Marinas | 1 | -1/+1 |
| 2018-03-27 | Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)" | Will Deacon | 1 | -3/+3 |
| 2018-03-09 | arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC | Shanker Donthineni | 1 | -0/+4 |
| 2018-03-06 | arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size) | Catalin Marinas | 1 | -3/+3 |
| 2017-03-20 | arm64: cache: Identify VPIPT I-caches | Will Deacon | 1 | -0/+7 |
| 2017-03-20 | arm64: cache: Merge cachetype.h into cache.h | Will Deacon | 1 | -1/+30 |
| 2015-10-28 | arm64: Increase the max granular size | Tirumalesh Chalamarla | 1 | -1/+1 |
| 2014-12-03 | arm64: Implement support for read-mostly sections | Jungseok Lee | 1 | -0/+2 |
| 2014-05-09 | arm64: Implement cache_line_size() based on CTR_EL0.CWG | Catalin Marinas | 1 | -1/+12 |
| 2012-09-17 | arm64: Cache maintenance routines | Catalin Marinas | 1 | -0/+32 |
