Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2018-05-15 | arm64: Increase ARCH_DMA_MINALIGN to 128 | Catalin Marinas | 1 | -2/+2 |
2018-05-11 | Revert "arm64: Increase the max granular size" | Catalin Marinas | 1 | -1/+1 |
2018-03-27 | Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)" | Will Deacon | 1 | -3/+3 |
2018-03-09 | arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC | Shanker Donthineni | 1 | -0/+4 |
2018-03-06 | arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size) | Catalin Marinas | 1 | -3/+3 |
2017-03-20 | arm64: cache: Identify VPIPT I-caches | Will Deacon | 1 | -0/+7 |
2017-03-20 | arm64: cache: Merge cachetype.h into cache.h | Will Deacon | 1 | -1/+30 |
2015-10-28 | arm64: Increase the max granular size | Tirumalesh Chalamarla | 1 | -1/+1 |
2014-12-03 | arm64: Implement support for read-mostly sections | Jungseok Lee | 1 | -0/+2 |
2014-05-09 | arm64: Implement cache_line_size() based on CTR_EL0.CWG | Catalin Marinas | 1 | -1/+12 |
2012-09-17 | arm64: Cache maintenance routines | Catalin Marinas | 1 | -0/+32 |