| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-02-11 | Merge branch 'locking/atomics' into locking/core, to pick up WIP commits | Ingo Molnar | 1 | -19/+19 |
| 2018-12-07 | arm64: Avoid masking "old" for LSE cmpxchg() implementation | Will Deacon | 1 | -2/+2 |
| 2018-12-07 | arm64: Avoid redundant type conversions in xchg() and cmpxchg() | Will Deacon | 1 | -23/+23 |
| 2018-11-01 | arm64, locking/atomics: Use instrumented atomics | Mark Rutland | 1 | -19/+19 |
| 2018-05-21 | arm64: lse: Add early clobbers to some input/output asm operands | Will Deacon | 1 | -12/+12 |
| 2017-07-20 | arm64: atomics: Remove '&' from '+&' asm constraint in lse atomics | Will Deacon | 1 | -1/+1 |
| 2017-05-09 | arm64: atomic_lse: match asm register sizes | Mark Rutland | 1 | -2/+2 |
| 2016-09-09 | arm64: lse: convert lse alternatives NOP padding to use __nops | Will Deacon | 1 | -37/+27 |
| 2016-06-16 | locking/atomic, arch/arm64: Implement atomic{,64}_fetch_{add,sub,and,andnot,o... | Will Deacon | 1 | -0/+172 |
| 2016-06-16 | locking/atomic, arch/arm64: Generate LSE non-return cases using common macros | Will Deacon | 1 | -90/+32 |
| 2016-02-26 | arm64: lse: deal with clobbered IP registers after branch via PLT | Ard Biesheuvel | 1 | -19/+19 |
| 2015-11-05 | arm64: cmpxchg_dbl: fix return value type | Lorenzo Pieralisi | 1 | -1/+1 |
| 2015-10-12 | arm64: atomics: implement native {relaxed, acquire, release} atomics | Will Deacon | 1 | -77/+116 |
| 2015-07-29 | arm64: lse: fix lse cmpxchg code indentation | Will Deacon | 1 | -3/+3 |
| 2015-07-27 | arm64: atomic64_dec_if_positive: fix incorrect branch condition | Will Deacon | 1 | -1/+1 |
| 2015-07-27 | arm64: atomics: implement atomic{,64}_cmpxchg using cmpxchg | Will Deacon | 1 | -43/+0 |
| 2015-07-27 | arm64: cmpxchg: avoid "cc" clobber in ll/sc routines | Will Deacon | 1 | -2/+2 |
| 2015-07-27 | arm64: cmpxchg_dbl: patch in lse instructions when supported by the CPU | Will Deacon | 1 | -0/+43 |
| 2015-07-27 | arm64: cmpxchg: patch in lse instructions when supported by the CPU | Will Deacon | 1 | -0/+39 |
| 2015-07-27 | arm64: atomics: patch in lse instructions when supported by the CPU | Will Deacon | 1 | -109/+291 |
| 2015-07-27 | arm64: introduce CONFIG_ARM64_LSE_ATOMICS as fallback to ll/sc atomics | Will Deacon | 1 | -0/+170 |
