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2025-07-01arm64: dts: imx8mp-venice-gw74xx: update name of M2SKT_WDIS2# gpioTim Harvey1-4/+4
The GW74xx D revision has added a M2SKT_WDIS2# GPIO which routes to the W_DISABLE2# pin of the M.2 socket. Update the gpio name for consistency. Fixes: 6a5d95b06d93 ("arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration") Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-01arm64: dts: freescale: imx93-tqma9352: add memory nodeMarkus Niebel1-0/+6
Although the bootloader should fixup with real memory size, add memory node here with smallest assembled size for readability. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-01arm64: dts: freescale: imx93-phyboard-nash: Move ADC vref to SoMPrimoz Fiser2-8/+13
Move configuration for ADC voltage reference from board DTS to a SoM include file. The SoC ADC reference voltage is connected to a "VDDA_1V8" voltage node and supplied by the PMIC's BUCK5 regulator. The reference voltage is thus defined by the SoM and cannot be changed by the carrier board design and as such belongs into the SoM include file. Moreover, with this in place, customers designing own carrier boards can simply include imx93-phycore-som.dtsi and enable adc1 in their own DTS without the need to define dummy ADC vref regulator themselves anymore. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20CJonas Karlman1-0/+1
eMMC HS200 mode (1.8V I/O) is supported by the MMC host controller on RK3528 and works with the optional on-board eMMC module on Radxa E20C. Be explicit about HS200 support in the device tree for Radxa E20C. Fixes: 3a01b5f14a8a ("arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250621165832.2226160-1-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-30arm64: dts: rockchip: Add bluetooth support to ArmSoM Sige7Jianfeng Liu1-0/+36
ArmSoM Sige7 has onboard AP6275P Wi-Fi6 (PCIe) and BT5 (UART) module which is similar with Khadas Edge2. This commit enables bluetooth at uart6. Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Link: https://lore.kernel.org/r/20250621135319.61766-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-30arm64: dts: rockchip: enable PCIe on ROCK 4DNicolas Frattaroli1-0/+15
The RADXA ROCK 4D board has a PCIe controller connected to a flat flex connector, compatible with the one the RPi5 uses. Enable the associated combphy and pcie controller node, as well as add the remaining pinctrl definition for the reset. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250621-rk3576-rock4d-pcie-v1-1-2b33c9f12955@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-30arm64: dts: rockchip: Enable HDMI receiver on CM3588Valentin Hăloiu1-0/+17
Enable support for the HDMI input port found on FriendlyElec CM3588 and CM3588 Plus. Signed-off-by: Valentin Hăloiu <valentin.haloiu@gmail.com> Link: https://lore.kernel.org/r/20250622185814.35031-1-valentin.haloiu@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-30arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576Cristian Ciocaltea1-2/+4
Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi"), the workaround of passing the rate from DW HDMI QP bridge driver via phy_set_bus_width() became partially broken, as it cannot reliably handle mode switches anymore. Attempting to fix this up at PHY level would not only introduce additional hacks, but it would also fail to adequately resolve the display issues that are a consequence of the system CRU limitations. Instead, proceed with the solution already implemented for RK3588: make use of the HDMI PHY PLL as a better suited DCLK source for VOP2. This will not only address the aforementioned problem, but it should also facilitate the proper operation of display modes up to 4K@60Hz. It's worth noting that anything above 4K@30Hz still requires high TMDS clock ratio and scrambling support, which hasn't been mainlined yet. Fixes: d74b842cab08 ("arm64: dts: rockchip: Add vop for rk3576") Cc: stable@vger.kernel.org Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Tested-By: Detlev Casanova <detlev.casanova@collabora.com> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-30arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576Cristian Ciocaltea1-0/+1
As with the RK3588 SoC, the HDMI PHY PLL on RK3576 can be used as a more accurate pixel clock source for VOP2, which is actually mandatory to ensure proper support for display modes handling. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI PHY. Fixes: ad0ea230ab2a ("arm64: dts: rockchip: Add hdmi for rk3576") Cc: stable@vger.kernel.org Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-2-4b11007d8675@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-30arm64: dts: rockchip: Add missing fan-supply to rk3566-quartz64-aDiederik de Haas1-0/+1
The Quartz 64 Model-A Schematic from 20210427 on page 7 shows that the fan's power supply is provided by VCC12V_DCIN. This fixes the following warning: gpio-fan gpio_fan: supply fan not found, using dummy regulator Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250628142843.839150-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-30arm64: dts: rockchip: use cs-gpios for spi1 on ringneckJakob Unterwurzacher1-0/+23
Hardware CS has a very slow rise time of about 6us, causing transmission errors when CS does not reach high between transaction. It looks like it's not driven actively when transitioning from low to high but switched to input, so only the CPU pull-up pulls it high, slowly. Transitions from high to low are fast. On the oscilloscope, CS looks like an irregular sawtooth pattern like this: _____ ^ / | ^ /| / | /| / | / | / | / | / | ___/ |___/ |_____/ |___ With cs-gpios we have a CS rise time of about 20ns, as it should be, and CS looks rectangular. This fixes the data errors when running a flashcp loop against a m25p40 spi flash. With the Rockchip 6.1 kernel we see the same slow rise time, but for some reason CS is always high for long enough to reach a solid high. The RK3399 and RK3588 SoCs use the same SPI driver, so we also checked our "Puma" (RK3399) and "Tiger" (RK3588) boards. They do not have this problem. Hardware CS rise time is good. Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Cc: stable@vger.kernel.org Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> Link: https://lore.kernel.org/r/20250627131715.1074308-1-jakob.unterwurzacher@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-30arm64: dts: exynos: gs101: switch to gs101 specific rebootAndré Draszik2-4/+2
gs101 (Google Pixel 6 and Pixel 6 Pro) supports cold- and warm-reboot. Cold-reset is useful because it is more secure, e.g. wiping all RAM contents, while the warm-reboot allows RAM contents to be retained across the reboot, e.g. to collect potential crash information. Add the required DT changes to switch to the gs101-specific reboot method, which knows how to issue either reset as requested by the OS. The PMIC plays a role in this as well, so mark it as 'system-power-controller', which in this case ensures that the device will wake up again after a cold-reboot, ensuring the full power-cycle is successful. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250627-gs101-reboot3-v1-3-c3ae49657b1f@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-30arm64: dts: exynos: gs101-pixel-common: add main PMIC nodeAndré Draszik1-0/+19
On Pixel 6 (and Pro), a Samsung S2MPG10 is used as main PMIC, which contains the following functional blocks: * common / speedy interface * regulators * 3 clock outputs * RTC * power meters * GPIO interfaces This change enables the PMIC itself and the RTC. We're still working on the remaining parts or waiting for bindings to be merged, hence only a small subset of the functional is being enabled. The regulators fall into the same category (still being finalised), but since the binding requires a 'regulators' node, an empty node is being added to avoid validation errors at this stage. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250627-gs101-reboot3-v1-2-c3ae49657b1f@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-30arm64: dts: exynos: gs101: ufs: add dma-coherent propertyPeter Griffin1-0/+1
ufs-exynos driver configures the sysreg shareability as cacheable for gs101 so we need to set the dma-coherent property so the descriptors are also allocated cacheable. This fixes the UFS stability issues we have seen with the upstream UFS driver on gs101. Fixes: 4c65d7054b4c ("arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes") Cc: stable@vger.kernel.org Suggested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Tested-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250314-ufs-dma-coherent-v1-1-bdf9f9be2919@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-30arm64: dts: add big-endian property back into watchdog nodeMeng Li1-1/+2
Watchdog doesn't work on NXP ls1046ardb board because in commit 7c8ffc5555cb("arm64: dts: layerscape: remove big-endian for mmc nodes"), it intended to remove the big-endian from mmc node, but the big-endian of watchdog node is also removed by accident. So, add watchdog big-endian property back. In addition, add compatible string fsl,ls1046a-wdt, which allow big-endian property. Fixes: 7c8ffc5555cb ("arm64: dts: layerscape: remove big-endian for mmc nodes") Cc: stable@vger.kernel.org Signed-off-by: Meng Li <Meng.Li@windriver.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx95-15x15-evk: fix the overshoot issue of NETCWei Fang1-10/+10
The overshoot of MDIO, MDC, ENET1_TDx and ENET2_TDx is too high, so reduce the drive strength of these pins. Fixes: e3e8b199aff8 ("arm64: dts: imx95: Add imx95-15x15-evk support") Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx95-19x19-evk: fix the overshoot issue of NETCWei Fang1-6/+6
The overshoot of MDIO, MDC and ENET1_TDx is too high, so reduce the drive strength these pins. Fixes: 025cf78938c2 ("arm64: dts: imx95-19x19-evk: add ENETC 0 support") Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx95: add SMMU support for NETCWei Fang2-0/+16
The i.MX95 NETC supports SMMU, so add SMMU support. Signed-off-by: Wei Fang <wei.fang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx943-evk: Add PDM microphone sound card supportShengjiu Wang1-0/+60
Add PDM micphone sound card support, configure the pinmux. This sound card supports recording sound from PDM microphone and convert the PDM format data to PCM data. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx943-evk: add bt-sco sound card supportShengjiu Wang1-0/+56
Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx943-evk: add sound-wm8962 supportShengjiu Wang1-0/+79
Add WM8962 codec connected to SAI1 interface. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx943-evk: add i2c io expander supportCarlos Song1-0/+105
Add i2c io expander support for imx943 evk board. Signed-off-by: Carlos Song <carlos.song@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx943-evk: add lpi2c supportCarlos Song1-0/+132
Add lpi2c and i2c-mux support for imx943 evk board. Signed-off-by: Carlos Song <carlos.song@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm64: dts: imx94: Add micfil and mqs device nodesShengjiu Wang1-0/+30
Add micfil and mqs device nodes Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-27arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-modeAndré Draszik1-0/+1
On gs101, the boot mode is stored both in a syscon register, and in nvmem. Add the dm-verity-device-corrupted reboot mode to the syscon-reboot- based boot mode as well, as both (nvmem & syscon) modes should be in sync. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-4-b479542eb97d@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-27arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-modeAndré Draszik1-1/+16
Add the 'nvmem-reboot-mode' which is used to communicate a requested boot mode to the boot loader. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-3-b479542eb97d@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-27arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMICAndré Draszik1-0/+61
On Pixel 6 (and Pro), a MAX77759 companion PMIC for USB Type-C applications is used, which contains four functional blocks (at distinct I2C addresses): * top (including GPIO & NVMEM) * charger * fuel gauge * TCPCi This change adds the PMIC and the subnodes for the GPIO expander and NVMEM, and defines the NVMEM layout. The NVMEM layout is declared such that it matches downstream's open-coded configuration [1]. Note: The pinctrl nodes are kept sorted by the 'samsung,pins' property rather than node name, as I think that makes it easier to look at and to add new nodes unambiguously in the future. Its label is prefixed with 'if' (for interface), because there are three PMICs in total in use on Pixel 6 (Pro). Link: https://android.googlesource.com/kernel/google-modules/bms/+/96e729a83817/max77759_maxq.c#67 [1] Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-2-b479542eb97d@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-26arm64: dts: qcom: x1-asus-zenbook: support soundAleksandrs Vinarskis1-0/+194
Works: * Both speakers * Both MICs * Headphones jack, L/R channels * Headphones jack, MIC Now working/untested: * Sound over DisplayPort * Sound over HDMI Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250623113709.21184-3-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-26arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodesAleksandrs Vinarskis3-5/+9
It appears not the latest version of the patch was merged. Align with latest upstreamed version by correcting GPU enable location and typo in GPU firmware path for x1p42100 variant. Fixes: 6516961352a1 ("arm64: dts: qcom: Add support for X1-based Asus Zenbook A14") Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250623113709.21184-2-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-26arm64: dts: renesas: r9a09g047: Add GBETH nodesJohn Madieu1-0/+209
Add GBETH nodes to RZ/G3E (R9A09G047) SoC DTSI. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Link: https://lore.kernel.org/20250623080405.355083-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-26arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Rename fixed regulator node namesLad Prabhakar1-2/+2
Rename "regulator0" to "regulator-0p8v" and "regulator1" to "regulator-3p3v" for consistency as done in the RZ/V2N EVK. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250620121045.56114-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-26arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add RAA215300 PMICLad Prabhakar1-0/+15
Add support for the Renesas RAA215300 PMIC to the RZ/V2N EVK. The PMIC is connected to I2C8 and uses a 32.768kHz fixed clock source (x6). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250619135539.207828-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-26arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add RAA215300 PMICLad Prabhakar1-0/+15
Add support for the Renesas RAA215300 PMIC to the RZ/V2H EVK. The PMIC is connected to I2C8 and uses a 32.768kHz fixed clock source (x6). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250619135539.207828-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-26arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE1 nodeParth Pancholi1-0/+5
The ACSPCIE1 module on TI's J784S4 SoC is capable of driving the reference clock required by the PCIe Endpoint device. It is an alternative to on- board and external reference clock generators. Add the device-tree node for the same. Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Link: https://lore.kernel.org/r/20250513152155.1590689-1-parth105105@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-26arm64: dts: ti: k3-j722s-evm: Fix USB gpio-hog level for Type-CSiddharth Vadapalli1-1/+1
According to the "GPIO Expander Map / Table" section of the J722S EVM Schematic within the Evaluation Module Design Files package [0], the GPIO Pin P05 located on the GPIO Expander 1 (I2C0/0x23) has to be pulled down to select the Type-C interface. Since commit under Fixes claims to enable the Type-C interface, update the property within "p05-hog" from "output-high" to "output-low", thereby switching from the Type-A interface to the Type-C interface. [0]: https://www.ti.com/lit/zip/sprr495 Cc: stable@vger.kernel.org Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250623100657.4082031-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-25arm64: dts: qcom: sm6115: add debug UART pinsBartosz Golaszewski1-0/+9
We should not rely on the bootloader to set up the pinmux of the debug UART port. Let's add pin definitions for uart4 to tlmm and bind them to the relevant device node. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20250625152839.193672-1-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-25arm64: dts: exynos5433: Align i2c-gpio node names with dtschemaKrzysztof Kozlowski1-1/+1
New dtschema v2025.6 enforces different naming on I2C nodes thus new dtbs_check warnings appeared for I2C GPIO nodes: exynos5433-tm2.dtb: i2c-gpio-0 (i2c-gpio): $nodename:0: 'i2c-gpio-0' does not match '^i2c(@.+|-[a-z0-9]+)?$' exynos5433-tm2.dtb: i2c-gpio-0 (i2c-gpio): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'amplifier@31' were unexpected) Rename the nodes to a generic i2c-[0-9]+ style with numbers continuing the SoC I2C controller indexing (3 controllers) for simplicity and obviousness, even if the SoC I2C controller is not enabled on given board. The names anyway would not conflict with SoC ones because of unit addresses. Verified with comparing two fdt (after fdtdump). Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Closes: https://lore.kernel.org/all/aCtD7BH5N_uPGkq7@shikoro/ Link: https://lore.kernel.org/r/20250612095549.77954-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-21arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PCHsun Lai2-0/+841
The Firefly ROC-RK3588S-PC is a SBC based on the Rockchip RK3588s SoC. Link: https://wiki.t-firefly.com/en/Station-M3/index.html The device contains the following hardware that is tested/working: - 32 or 64GB eMMC - SDMMC card slot - Realtek USB WiFi 5/BT - NVME 2242 socket - 4 or 8GB of RAM - RTL8211 GbE - USB 3.0 port - USB 2.0 port - HDMI port Signed-off-by: Hsun Lai <i@chainsx.cn> Link: https://lore.kernel.org/r/20250609113044.8846-3-i@chainsx.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-21arm64: dts: rockchip: Enable GPU on Radxa E20CJonas Karlman1-0/+5
Enable the Mali-450 MP2 GPU on the Radxa E20C. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250518225418.682182-4-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-21arm64: dts: rockchip: Add GPU node for RK3528Jonas Karlman1-0/+58
Add a GPU node and a opp-table for the Mali-450 MP2 in the RK3528 SoC. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250518225418.682182-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-21arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"Hrushikesh Salunke1-0/+1
AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be functional at all stages of PCIe boot process. Thus add the "bootph-all" boot phase tag to "pcie0_ep" device tree node. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250610054920.2395509-1-h-salunke@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-j722s-main: Add audio-refclk0 nodeMichael Walle1-0/+9
Add the node for the AUDIO_EXT_REFCLK0 clock output. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20250618090724.1917731-1-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62p-j722s: fix pinctrl-single sizeMichael Walle1-1/+1
Pinmux registers ends at 0x000f42ac (including). Thus, the size argument of the pinctrl-single node has to be 0x2b0. Fix it. This will fix the following error: pinctrl-single f4000.pinctrl: mux offset out of range: 0x2ac (0x2ac) Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs") Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20250618065239.1904953-1-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62a7-sk: Describe the SPI NANDMiquel Raynal1-0/+42
Describe the octal SPI NAND available on the low-power starter kit. The pinctrl configuration comes from TI fork. With the current mainline tree, we currently get the following performances: eraseblock write speed is 7507 KiB/s eraseblock read speed is 15802 KiB/s page write speed is 7551 KiB/s page read speed is 15609 KiB/s 2 page write speed is 7551 KiB/s 2 page read speed is 15609 KiB/s erase speed is 284444 KiB/s 2x multi-block erase speed is 512000 KiB/s Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20250613182356.1272642-1-miquel.raynal@bootlin.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-j721s2-main: Add McASP nodesJayesh Choudhary1-0/+90
Add McASP 0-4 instances and keep them disabled because several required properties are missing as they are board specific. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20250604104656.38752-2-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62p-verdin: Enable pull-ups on I2C_3_HDMIEmanuele Ghidoli1-2/+2
Enable internal bias pull-ups on the SoC-side I2C_3_HDMI that do not have external pull resistors populated on the SoM. This ensures proper default line levels. Fixes: 87f95ea316ac ("arm64: dts: ti: Add Toradex Verdin AM62P") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250529102601.452859-1-ghidoliemanuele@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62-verdin: Enable pull-ups on I2C busesEmanuele Ghidoli1-6/+6
Enable internal bias pull-ups on the SoC-side I2C buses that do not have external pull resistors populated on the SoM. This ensures proper default line levels. Cc: stable@vger.kernel.org Fixes: 316b80246b16 ("arm64: dts: ti: add verdin am62") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250528110741.262336-1-ghidoliemanuele@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet portsWadim Egorov1-0/+2
For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must be supplied on CLKOUT0. Previously, our bootloader configured this clock, which is why the PRU Ethernet ports appeared to work, but the change never made it into the device tree. Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Fixes: 87adfd1ab03a ("arm64: dts: ti: am642-phyboard-electra: Add PRU-ICSSG nodes") Link: https://lore.kernel.org/r/20250521053339.1751844-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-20arm64: dts: mediatek: mt8370: Enable gpu supportLouis-Alexis Eyraud1-0/+16
Add a new gpu node in mt8370.dtsi to enable support for the ARM Mali G57 MC2 GPU (Valhall-JM) found on the MT8370 SoC, using the Panfrost driver. On a Mediatek Genio 510 EVK board, the panfrost driver probed with the following message: ``` panfrost 13000000.gpu: clock rate = 390000000 panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x0 status 0x0 panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000003, 80000400 panfrost 13000000.gpu: Features: L2:0x08130206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7 panfrost 13000000.gpu: shader_present=0x5 l2_present=0x1 [drm] Initialized panfrost 1.3.0 for 13000000.gpu on minor 0 ``` Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://lore.kernel.org/r/20250509-mt8370-enable-gpu-v6-5-2833888cb1d3@collabora.com
2025-06-20arm64: dts: rockchip: support camera module on Haikou Video Demo on PX30 ↵Quentin Schulz1-0/+53
Ringneck The Haikou Video Demo adapter has a proprietary connector for a camera module which has an OV5675 camera sensor and a companion DW9714 focus lens driver. This adds support for the camera module on PX30 Ringneck module fitted on a Haikou devkit with the Haikou Video Demo adapter. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250610-ringneck-haikou-video-demo-cam-v2-3-de1bf87e0732@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 01:07:20 +0300