summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/renesas
AgeCommit message (Collapse)AuthorFilesLines
2023-03-10arm64: dts: renesas: beacon-renesom: Fix gpio expander referenceAdam Ford1-14/+10
[ Upstream commit d7f9492dfc03153ac56ab59066a196558748f575 ] The board used to originally introduce the Beacon Embedded RZ/G2[M/N/H] boards had a GPIO expander with address 20, but this was changed when the final board went to production. The production boards changed both the part itself and the address. With the incorrect address, the LCD cannot come up. If the LCD fails, the rcar-du driver fails to come up, and that also breaks HDMI. Pre-release board were not shipped to the general public, so it should be safe to push this as a fix. Anyone with a production board would have video fail due to this GPIO expander change. Fixes: a1d8a344f1ca ("arm64: dts: renesas: Introduce r8a774a1-beacon-rzg2m-kit") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230114225647.227972-1-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-13Merge tag 'media/v6.2-1' of ↵Linus Torvalds1-1/+0
git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media updates from Mauro Carvalho Chehab: - DVB core changes to avoid refcount troubles and UAF - DVB API/core has gained support for DVB-C2 and DVB-S2X - New sensor drivers: ov08x40, ov4689.c, st-vgxy61 and tc358746.c - Removal of an unused sensor driver: s5k4ecgx - Move microchip_csi2dc to a new directory, named after the manufacturer - Add media controller support to Microship drivers - Old Atmel/Microship drivers that don't use media controler got moved to staging - New drivers added for Renesas RZ/G2L CRU and MIPI CSI-2 support - Allwinner A31 camera sensor driver code was now split into a bridge and a separate processor driver - Added a virtual stateless decoder driver in order to test core support for stateless drivers and test userspace apps using it - removed platform-based support for ov9650, as this is not used anymore - atomisp now uses videobuf2 and supports normal mmap mode - the imx7-media-csi driver got promoted from staging - rcar-vin driver has gained support for gen3 UDS (Up Down Scaler) - most i2c drivers now use I2C .probe_new() kAPI - lots of drivers fixes, cleanups and improvements * tag 'media/v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (544 commits) media: s5c73m3: Switch to GPIO descriptors media: i2c: s5k5baf: switch to using gpiod API media: i2c: s5k6a3: switch to using gpiod API media: imx: remove code for non-existing config IMX_GPT_ICAP media: si470x: Fix use-after-free in si470x_int_in_callback() media: staging: stkwebcam: Restore MEDIA_{USB,CAMERA}_SUPPORT dependencies media: coda: Add check for kmalloc media: coda: Add check for dcoda_iram_alloc dt-bindings: media: s5c73m3: Fix reset-gpio descriptor media: dt-bindings: allwinner: h6-vpu-g2: Add IOMMU reference property media: s5k4ecgx: Delete driver media: s5k4ecgx: Switch to GPIO descriptors media: Switch to use dev_err_probe() helper headers: Remove some left-over license text in include/uapi/linux/v4l2-* headers: Remove some left-over license text in include/uapi/linux/dvb/ media: usb: pwc-uncompress: Use flex array destination for memcpy() media: s5p-mfc: Fix to handle reference queue during finishing media: s5p-mfc: Clear workbit to handle error condition media: s5p-mfc: Fix in register read and write for H264 media: imx: Use get_mbus_config instead of parsing upstream DT endpoints ...
2022-11-25media: arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Drop clock-names ↵Lad Prabhakar1-1/+0
property Now that the driver has been updated to drop fetching the clk reference by name we no longer need the clock-names property in the ov5645 sensor node. This is in preparation for removal for clock-names property from the DT binding. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-11-21arm64: dts: renesas: Rename DTB overlay source files from .dts to .dtsoAndrew Davis2-0/+0
DTB Overlays (.dtbo) can now be built from source files with the extension (.dtso). This makes it clear what is the content of the files and differentiates them from base DTB source files. Convert the DTB overlay source files in the arm64/renesas directory. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20221024173434.32518-6-afd@ti.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-18arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDESYoshihiro Shimoda1-0/+90
Enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221118120953.1186392-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-18arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodesYoshihiro Shimoda1-0/+110
Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221118120953.1186392-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17arm64: dts: renesas: r9a09g011: Add system controller nodeBiju Das1-0/+5
Add system controller node to RZ/V2M SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221116102140.852889-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17arm64: dts: renesas: r8a779g0: Add CA76 operating pointsGeert Uytterhoeven1-0/+31
Add operating points for running the Cortex-A76 CPU cores on R-Car V4H at various speeds, up to the Normal (1.7 GHz) performance mode. Based on a patch in the BSP by Tho Vu. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8afb32f5dc123ebf2b941703483152ff0992191d.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add CPU core clocksGeert Uytterhoeven1-0/+4
Describe the clocks for the four Cortex-A76 CPU cores. CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/aa6e9ae21e451ebd40d54d986bd0296571128d5b.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add CPUIdle supportGeert Uytterhoeven1-0/+17
Support CPUIdle for ARM Cortex-A76 on R-Car V4H. Based on patches in the BSP by Tho Vu and Vincent Bryce. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f6d4076983eb45cf23595a045747f28cbdcdf4e6.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU coresGeert Uytterhoeven1-5/+65
Complete the description of the Cortex-A76 CPU cores and L3 cache controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU topology and PSCI support for enabling CPU cores. R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters. Based on a patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ccb55458bd87f8ba70d28c61bcc254f22184824c.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add L3 cache controllerGeert Uytterhoeven1-0/+8
Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
2022-11-15arm64: dts: renesas: r9a09g011: Add L2 Cache nodeBiju Das1-0/+7
The Cortex-A53 processor on RZ/V2M has 512 KB L2 Cache. Add L2 Cache node to SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221110160931.101539-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-15arm64: dts: renesas: rzv2mevk2: Enable watchdogFabrizio Castro1-0/+4
Enable the watchdog so that we can reboot the system. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20221103223956.50575-4-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-15arm64: dts: renesas: r9a09g011: Add watchdog nodeFabrizio Castro1-0/+13
The r9a09g011 (a.k.a. RZ/V2M) comes with two watchdog IPs, but Linux is only allowed one. Add a node for the watchdog allowed to Linux to the SoC specific dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20221103223956.50575-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-10arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0Wolfram Sang1-15/+15
Every loader before Linux utilizes HSCIF0 with a speed of 1843200 bps. Make Linux behave the same. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220613131033.10053-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodesLad Prabhakar2-2/+0
This fixes the below dtbs_check warning: arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml Drop #address-cells properties from pinctrl nodes as they have no addressed child nodes. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20221107172953.63218-1-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20221107172953.63218-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: r9a09g011: Fix I2C SoC specific stringsFabrizio Castro1-2/+2
The preferred form for Renesas' compatible strings is: "<vendor>,<family>-<module>" Somehow the compatible string for the r9a09g011 I2C IP was upstreamed as renesas,i2c-r9a09g011 instead of renesas,r9a09g011-i2c, which is really confusing, especially considering the generic fallback is renesas,rzv2m-i2c. The first user of renesas,i2c-r9a09g011 in the kernel is not yet in a kernel release, it will be in v6.1, therefore it can still be fixed in v6.1. Even if we don't fix it before v6.2, I don't think there is any harm in making such a change. s/renesas,i2c-r9a09g011/renesas,r9a09g011-i2c/g for consistency. Fixes: 54ac6794df9d ("arm64: dts: renesas: r9a09g011: Add i2c nodes") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20221107165027.54150-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: rzg2l: Add missing cache-level propertiesPierre Gondois3-0/+3
The DeviceTree Specification v0.3 specifies that the cache node 'cache-level' property is 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes. Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Link: https://lore.kernel.org/r/20221107155825.1644604-19-pierre.gondois@arm.com [geert: Update description] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: r8a779g0: Add CMT nodeThanh Quan1-0/+70
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> [wsa: merged the fixes into this one and rebased] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221104151135.4706-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: r9a09g011: Fix unit address format errorFabrizio Castro1-1/+1
Although the HW User Manual for RZ/V2M states in the "Address Map" section that the interrupt controller is assigned addresses starting from 0x82000000, the memory locations from 0x82000000 0x0x8200FFFF are marked as reserved in the "Interrupt Controller (GIC)" section and are currently not used by the device tree, leading to the below warning: arch/arm64/boot/dts/renesas/r9a09g011.dtsi:51.38-63.5: Warning (simple_bus_reg): /soc/interrupt-controller@82000000: simple-bus unit address format error, expected "82010000" Fix the unit address accordingly. Fixes: fb1929b98f2e ("arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20221103230648.53748-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: white-hawk-cpu: Sort RWDT entry correctlyWolfram Sang1-4/+4
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221103205546.24836-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: r8a779g0: Add TMU nodesWolfram Sang1-0/+65
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221103205546.24836-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clockWolfram Sang1-4/+4
As serial communication requires a clean clock signal, the Serial Communication Interfaces with FIFO (SCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the clock input for the SCIF Baud Rate Generator internal clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81. Fixes: c62331e8222f ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support") Fixes: 40753144256b ("arm64: dts: renesas: r8a779f0: Add SCIF nodes") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221103143440.46449-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clockWolfram Sang1-4/+4
As serial communication requires a clean clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the clock input for the HSCIF Baud Rate Generator internal clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81. Fixes: 01a787f78bfd ("arm64: dts: renesas: r8a779f0: Add HSCIF nodes") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221103143440.46449-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-28arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific partsLad Prabhakar2-53/+61
Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC). Below are the changes due to which SoC specific parts are moved to r9a07g043u.dtsi: - RZ/G2UL has Cortex-A55 (ARM64) whereas RZ/Five has AX45MP (RISC-V), - RZ/G2UL has GICv3 as interrupt controller whereas RZ/Five has PLIC, - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing for SYSC block on RZ/Five, - RZ/G2UL has armv8-timer whereas RZ/Five has riscv-timer, - RZ/G2UL has PSCI whereas RZ/Five have OpenSBI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-28arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to ↵Lad Prabhakar3-152/+163
specify interrupt property Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so that we can share the common parts of the SoC DTSI with the RZ/Five (RISC-V) SoC and the RZ/G2UL (ARM64) SoC. This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL (ARM64) SoC specific parts. No functional changes (same DTB). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221025220629.79321-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-28arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible valuesGeert Uytterhoeven1-12/+12
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible properties in various device nodes to include family-specific compatible values for R-Car Gen4 instead of R-Car Gen3: - EtherAVB, - MSIOF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/387168aef20d399d4f4318f4ecab9c3b016fd6f2.1666605756.git.geert+renesas@glider.be
2022-10-24arm64: dts: renesas: r8a779g0: Add remaining HSCIF nodesGeert Uytterhoeven1-3/+53
Add device nodes for the remaining High Speed Serial Communication Interfaces with FIFO (HSCIF) on the Renesas R-Car V4H (R8A779G0) SoC, including DMA support. Reformat the existing HSCIF0 node for consistency. Based on patches in the BSP by Takeshi Kihara and Vinh Nguyen. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/64c15b2d13439b2072cde0b588a251cb54f7dc01.1666361314.git.geert+renesas@glider.be
2022-10-24arm64: dts: renesas: r8a779g0: Add SCIF nodesGeert Uytterhoeven1-0/+68
Add device nodes for the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car V4H (R8A779G0) SoC, including DMA support. Based on patches in the BSP by Takeshi Kihara and Vinh Nguyen. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3f0ad7ce0fedfca2783001a6eb3eca96aea72115.1666361314.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: white-hawk-cpu: Add QSPI FLASH supportHai Pham1-0/+33
Describe the QSPI FLASH on the White Hawk CPU board. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c3a01a8de924d6a3fcdb1ee0284544ad2ea5c8ec.1665583435.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: r8a779g0: Add RPC nodeHai Pham1-0/+16
Add a device node for the SPI Multi I/O Bus Controller (RPC-IF) on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/6da7a035d56a943336f68dc0da77a47dba3dd69e.1665583435.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: white-hawk-cpu: Add eMMC supportTakeshi Kihara1-0/+41
Describe the eMMC on the White Hawk CPU board. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/253cd479e55486dd0d3e3804add405e41c32d53b.1665558371.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: r8a779g0: Add SDHI nodeGeert Uytterhoeven1-0/+14
Add a device node for the SD Card/MMC Interface on the Renesas R-Car V4H (R8A779G0) SoC. Based on a patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/d2d5cf982a380699483edf7a632441628ee73183.1665558371.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: rzg2l: Drop WDT2 nodesLad Prabhakar5-55/+0
On members of the RZ/G2L family, WDT CH2 is specifically meant to check the operation of the Cortex-M33 CPU. Using it from a Cortex-A55 CPU would result in unexpected behaviour. Hence drop all WDT2 nodes and their references from the affected SoC and SoM DTSI files. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-17arm64: dts: renesas: r8a779g0: Add TPU device nodeCongDang1-0/+11
Add a device node for the 16-Bit Timer Pulse Unit (TPU) on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: CongDang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/b98acb22fdd1bcc6a9ca8a4255f85e04c571975c.1665156417.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: r8a779g0: Add PWM device nodesCongDang1-0/+100
Add device nodes for the PWM timers on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: CongDang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6a2df8c9f751993ae40aa8f196f4124e384b0aab.1665156417.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clockGeert Uytterhoeven1-1/+1
As serial communication requires a clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the clock input for the HSCIF0 Baud Rate Generator internal clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/a5bd4148f92806f7c8e577d383370f810315f586.1665155947.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: condor-common: Add missing bootargsKuninori Morimoto1-0/+1
This patch adds missing bootargs for V3H Condor board. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87h70lhd1c.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-17arm64: dts: renesas: white-hawk-cpu: Add PCA9654 I/O ExpanderGeert Uytterhoeven1-0/+11
Describe the PCA9654 I/O Expander on the White Hawk CPU board. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e75ea6feaedc013c504a032a6cf1cb7dd809ce27.1664369170.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: r8a779g0: Add INTC-EX nodeGeert Uytterhoeven1-0/+16
Add the device node for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car V4H (R8A779G0) SoC, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f2e5adf62a7666db7350d9596a907bc7f9e81d43.1664369015.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: r8a779g0: Add MSIOF nodesGeert Uytterhoeven1-0/+96
Add device nodes for the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car V4H (R8A779G0) SoC, including DMA support. Based on patches in the BSP by Thanh Quan. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/450921ef6d8c30ca2953a1665c8597f6a69d01f2.1664204771.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: r8a779g0: Add DMA supportGeert Uytterhoeven1-0/+91
Add device nodes for the Direct Memory Access Controllers for System (SYS-DMAC) on the Renesas R-Car V4H (R8A779G0) SoC. Link all DMA consumers to the corresponding DMA controller channels. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1ea45b51f897a11d9477be4ac54fdb0efcc624e1.1664204771.git.geert+renesas@glider.be
2022-10-17arm64: dts: renesas: rzg2ul-smarc: Move spi1 pinmux to carrier board DTSILad Prabhakar2-7/+7
spi1 is available on the RZ/G2UL SMARC EVK carrier board (PMOD0), hence moving the spi1 pinmux from SoM to carrier board. This is to keep consistency with the other SMARC EVKs. Also while moving the pinmux rename rspi1 to spi1 to be consistent with other SMARC EVK DTSIs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220921082221.10599-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-17arm64: dts: renesas: rzg2lc-smarc: Include SoM DTSI into board DTSLad Prabhakar2-28/+30
Move including the rzg2lc-smarc-som.dtsi from the carrier board rzg2lc-smarc.dtsi to the actual RZ/G2LC SMARC EVK board dts r9a07g044c2-smarc.dts. Also move the SW1 related macros along with PMOD1_SER0 to board dts so that we have all the configuration options in the same file. This patch is to keep consistency with other SMARC EVKs (RZ/G2L, RZ/G2UL) and it makes sense not include the SoM into the carrier board as we might in future have a different carrier board with the same SoM. Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220919092130.93074-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-08Merge tag 'clk-for-linus' of ↵Linus Torvalds2-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have some late breaking reports that a patch series to rework clk rate range support broke boot on some devices, so I've left that branch out of this. Hopefully we can get to that next week, or punt on it and let it bake another cycle. That means we don't really have any changes to the core framework this time around besides a few typo fixes. Instead this is all clk driver updates and fixes. The usual suspects are here (again), with Qualcomm dominating the diffstat. We look to have gained support for quite a few new Qualcomm SoCs and Dmitry worked on updating many of the existing Qualcomm drivers to use clk_parent_data. After that we have MediaTek drivers getting some much needed updates, in particular to support GPU DVFS. There are also quite a few Samsung clk driver patches, but that's mostly because there was a maintainer change and so last release we missed some of those patches. Overall things look normal, but I'm slowly reviewing core framework code nowadays and that shows given the rate range patches had to be yanked last minute. Let's hope this situation changes soon. New Drivers: - Support for Renesas VersaClock7 clock generator family - Add Spreadtrum UMS512 SoC clk support - New clock drivers for MediaTek Helio X10 MT6795 - Display clks for Qualcomm SM6115, SM8450 - GPU clks for Qualcomm SC8280XP - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers Deleted Drivers: - Remove DaVinci DM644x and DM646x clk driver support Updates: - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - More devm helpers for fixed rate registration - Various PXA168 clk driver fixes - Add resets for MediaTek MT8195 PCIe and USB - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek - Shrink MT8192 clock driver by deduplicating clock parent lists - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk' clocks for i.MX8MP - Drop unnecessary newline in i.MX8MM dt-bindings - Add more MU1 and SAI clocks dt-bindings Ids - Introduce slice busy bit check for i.MX93 composite clock - Introduce white list bit check for i.MX93 composite clock - Add new i.MX93 clock gate - Add MU1 and MU2 clocks to i.MX93 clock provider - Add SAI IPG clocks to i.MX93 clock provider - add generic clocks for U(S)ART available on SAMA5D2 SoCs - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8 - Add I2C clocks and resets on RZ/V2M - Document clock support for the RZ/Five SoC - mux-variant clock using the table variant to select parents - clock controller for the rv1126 soc - conversion of rk3128 to yaml and relicensing of the yaml bindings to gpl2+MIT (following dt-binding guildelines) - Exynos7885: add FSYS, TREX and MFC clock controllers - Exynos850: add IS and AUD (audio) clock controllers with bindings - ExynosAutov9: add FSYS clock controllers with bindings - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock controllers, due to duplicated entries. This is an acceptable ABI break: recently developed/added platform so without legacies, acked by known users/developers - ExynosAutov9: add few missing Peric 0/1 gates - ExynosAutov9: correct register offsets of few Peric 0/1 clocks - Minor code improvements (use of_device_get_match_data() helper, code style) - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he already maintainers that architecture/platform - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration - Qualcomm SDM660 SDCC1 moved to floor clk ops - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was added/fixed - The Qualcomm MSM8996 CPU clocks are updated with support for ACD - Support for Qualcomm SDM670 GCC and RPMh clks was added - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for many Qualcomm SoCs - Support for per-reset defined delay on Qualcomm was introduced" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: ast2600: BCLK comes from EPLL clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: nxp: fix typo in comment clk: pxa: add a check for the return value of kzalloc() clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: imx: scu: fix memleak on platform_device_add() fails clk: vc5: Use regmap_{set,clear}_bits() where appropriate ...
2022-09-19arm64: dts: renesas: Adjust whitespace around '{'Lad Prabhakar3-3/+3
Drop extra space around the '{' sign. No functional changes (same DTB). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220916100251.20329-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-19arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTSLad Prabhakar2-11/+12
Move including the rzg2ul-smarc-som.dtsi from the carrier board rzg2ul-smarc.dtsi to the actual RZ/G2UL SMARC EVK board dts r9a07g043u11-smarc.dts. Also move the SW_SW0_DEV_SEL and SW_ET0_EN_N macros to board dts as they are used by SoM and carrier board DTS/I. This is in preparation of re-using the SoM and carrier board DTSIs for RZ/Five SMARC EVK. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220915165256.352843-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-19arm64: dts: renesas: rzg2ul-smarc-som: Drop enabling wdt2Lad Prabhakar1-5/+0
WDT CH2 is specifically to check the operation of Cortex-M33 CPU so don't enable WDT2 by default. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220914134211.199631-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-19arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible valuesGeert Uytterhoeven1-5/+5
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible properties in various device nodes to include family-specific compatible values for R-Car Gen4 instead of R-Car Gen3: - CMT, - SDHI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f14fde21270bf8269a61a75fc6e50af2765f2a42.1663164707.git.geert+renesas@glider.be
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-02 09:04:22 +0300