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2020-11-25arm64: tegra: Fix Tegra234 VDK node namesJon Hunter1-3/+3
When the device-tree board file was added for the Tegra234 VDK simulator it incorrectly used the names 'cbb' and 'sdhci' instead of 'bus' and 'mmc', respectively. The names 'bus' and 'mmc' are required by the device-tree json-schema validation tools. Therefore, fix this by renaming these nodes accordingly. Fixes: 639448912ba1 ("arm64: tegra: Initial Tegra234 VDK support") Reported-by: Ashish Singhal <ashishsingha@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Wrong AON HSP reg property sizeDipen Patel1-1/+1
The AON HSP node's "reg" property size 0xa0000 will overlap with other resources. This patch fixes that wrong value with correct size 0x90000. Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Dipen Patel <dipenp@nvidia.com> Fixes: a38570c22e9d ("arm64: tegra: Add nodes for TCU on Tegra194") Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Fix USB_VBUS_EN0 regulator on Jetson TX1JC Kuo1-10/+10
USB host mode is broken on the OTG port of Jetson TX1 platform because the USB_VBUS_EN0 regulator (regulator@11) is being overwritten by the vdd-cam-1v2 regulator. This commit rearranges USB_VBUS_EN0 to be regulator@14. Fixes: 257c8047be44 ("arm64: tegra: jetson-tx1: Add camera supplies") Cc: stable@vger.kernel.org Signed-off-by: JC Kuo <jckuo@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Correct the UART for Jetson Xavier NXJon Hunter1-1/+1
The Jetson Xavier NX board routes UARTA to the 40-pin header and UARTC to a 12-pin debug header. The UARTs can be used by either the Tegra Combined UART (TCU) driver or the Tegra 8250 driver. By default, the TCU will use UARTC on Jetson Xavier NX. Currently, device-tree for Xavier NX enables the TCU and the Tegra 8250 node for UARTC. Fix this by disabling the Tegra 8250 node for UARTC and enabling the Tegra 8250 node for UARTA. Fixes: 3f9efbbe57bc ("arm64: tegra: Add support for Jetson Xavier NX") Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25arm64: tegra: Disable the ACONNECT for Jetson TX2Jon Hunter1-12/+0
Commit ff4c371d2bc0 ("arm64: defconfig: Build ADMA and ACONNECT driver") enable the Tegra ADMA and ACONNECT drivers and this is causing resume from system suspend to fail on Jetson TX2. Resume is failing because the ACONNECT driver is being resumed before the BPMP driver, and the ACONNECT driver is attempting to power on a power-domain that is provided by the BPMP. While a proper fix for the resume sequencing problem is identified, disable the ACONNECT for Jetson TX2 temporarily to avoid breaking system suspend. Please note that ACONNECT driver is used by the Audio Processing Engine (APE) on Tegra, but because there is no mainline support for APE on Jetson TX2 currently, disabling the ACONNECT does not disable any useful feature at the moment. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-10-24Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds15-12/+927
Pull ARM Devicetree updates from Olof Johansson: "As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits) ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users arm64: dts: lg: Fix SP805 clocks ARM: mstar: Fix up the fallout from moving the dts/dtsi files ARM: mstar: Add mstar prefix to all of the dtsi/dts files ARM: mstar: Add interrupt to pm_uart ARM: mstar: Add interrupt controller to base dtsi ARM: dts: meson8: remove two invalid interrupt lines from the GPU node arm64: dts: ti: k3-j7200-common-proc-board: Add USB support arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function arm64: dts: ti: k3-j7200-main: Add USB controller arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC ARM: dts: hisilicon: add SD5203 dts ARM: dts: hisilicon: fix the system controller compatible nodes arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 arm64: dts: zynqmp: Remove undocumented u-boot properties arm64: dts: zynqmp: Remove additional compatible string for i2c IPs arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml ...
2020-09-18arm64: tegra: Initial Tegra234 VDK supportThierry Reding3-0/+230
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-17arm64: tegra: Populate EEPROMs for Jetson Xavier NXJon Hunter2-0/+30
Populate the EEPROMs that are present on the Jetson Xavier NX developer platform. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-17arm64: tegra: Add label properties for EEPROMsJon Hunter7-0/+8
Populate the label property for the AT24 EEPROMs on the various Jetson platforms. Note that the name 'module' is used to identify the EEPROM on the processor module board and the name 'system' is used to identify the EEPROM on the main base board (which is sometimes referred to as the carrier board). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-02arm64: tegra: Add DT binding for AHUB componentsSameer Pujar3-2/+580
This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194. Bindings for following modules are added. * AHUB added as a child node under ACONNECT * AHUB includes many HW accelerators and below components are added as its children. * ADMAIF * I2S * DMIC * DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does not have this module) Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-02arm64: tegra: Enable ACONNECT, ADMA and AGIC on Jetson NanoSameer Pujar1-0/+12
These devices are required for audio sub system and current patch ensures probe path of these devices gets tested. Later sound card support would be added which can use these devices at runtime. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-28arm64: tegra: Add missing timeout clock to Tegra194 SDMMC nodesSowjanya Komatineni1-6/+9
commit 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree") Tegra194 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock is not enabled currently which is not recommended. Tegra194 SDMMC advertises 12Mhz as timeout clock frequency in host capability register. So, this clock should be kept enabled by SDMMC driver. Fixes: 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-7-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-08-28arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodesSowjanya Komatineni1-8/+12
commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support") Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock is not enabled currently which is not recommended. Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host capability register and uses it by default. So, this clock should be kept enabled by the SDMMC driver. Fixes: 39cb62cb8973 ("arm64: tegra: Add Tegra186 support") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-6-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-08-28arm64: tegra: Add missing timeout clock to Tegra210 SDMMCSowjanya Komatineni1-8/+12
commit 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support") Tegra210 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock is not enabled currently which is not recommended. Tegra SDMMC advertises 12Mhz as timeout clock frequency in host capability register. So, this clock should be kept enabled by SDMMC driver. Fixes: 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-5-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-08-27arm64: tegra: Properly size register regions for GPU on Tegra194Thierry Reding1-2/+2
Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather than 256 MiB. Reported-by: Terje Bergström <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-By: Terje Bergström <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-27arm64: tegra: Use valid PWM period for VDD_GPU on Tegra210Thierry Reding2-2/+2
The PWM on Tegra210 can run at a maximum frequency of 48 MHz and cannot reach the minimum period is 5334 ns. The currently configured period of 4880 ns is not within the valid range, so set it to 8000 ns. This value was taken from the downstream DTS files and seems to work fine. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-27arm64: tegra: Describe display controller outputs for Tegra210Thierry Reding1-4/+6
Both display controllers can drive both DSI and both SOR outputs on Tegra210. Describe this in device tree so that the operating system doesn't have to guess. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-27arm64: tegra: Disable SD card write-protection on Jetson NanoThierry Reding1-0/+1
There is no GPIO hooked up to the write-protection pin of the SD slot. Make sure to describe this properly in device tree to avoid errors or warnings being emitted by the operating system. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-27arm64: tegra: Add VBUS supply for micro USB port on Jetson NanoThierry Reding1-0/+12
The VBUS supply for the micro USB port on Jetson Nano is derived from the main system supply and always on. Describe in nevertheless to fix warnings during boot. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-27arm64: tegra: Wire up pinctrl states for all DPAUX controllersThierry Reding1-2/+16
All four DPAUX controllers on Tegra194 control the pin configuration of their companion I2C controllers. Wire up all the pinctrl states for the I2C controllers so that their pins can be correctly muxed when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-27arm64: tegra: Add ID EEPROMs on Jetson AGX XavierThierry Reding2-0/+28
The P2888 processor module contains an EEPROM that provides means of identifying the module. The P2822 carrier board contains the same EEPROM with information identifying the carrier board. Both of them ar accessed via the GEN_I2C1 bus. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-17arm64: tegra: Add the GPU on Tegra194Thierry Reding1-0/+34
The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called GV11B. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-16arm64: tegra: Add compatible string for Tegra194 CPU complexSumit Gupta1-0/+2
On Tegra194, data on valid operating points for the CPUs needs to be queried from BPMP. However, there is no node representing CPU complex. So, add a compatible string to the 'cpus' node instead of using dummy node to bind the cpufreq driver to. Also, add reference to the BPMP instance for the CPU complex. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-16arm64: tegra: Add HDMI supplies on NorrinThierry Reding1-0/+3
The SOR controller needs the AVDD I/O and VDD HDMI PLL supplies in order to operate correctly. Make sure to specify them for the Norrin board. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-16arm64: tegra: Add #{address,size}-cells for VI I2C on Tegra210Thierry Reding1-0/+3
The VI I2C controller provides an I2C bus and therefore needs to define the #address-cells and #size-cells properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-16arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2CSowjanya Komatineni1-0/+6
Tegra210 VI I2C is in VE power domain and i2c-vi node should have power-domains property. Current Tegra210 i2c-vi device node is missing both VI I2C clocks and power-domains property. This patch adds them. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Add clocks and resets for ISP on Tegra210Thierry Reding1-0/+6
The ISP blocks take a clock and a reset as inputs, so add those to the device tree nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix compatible string for DPAUX on Tegra210Thierry Reding1-1/+1
The Tegra210 DPAUX controller is not compatible with that found on Tegra124, so it must have a separate compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Add i2c-bus subnode for DPAUX controllersThierry Reding1-0/+5
The DPAUX controller device tree bindings require the bus to have an i2c-bus subnode to distinguish between I2C clients and pinmux groups. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Sort aliases alphabeticallyThierry Reding2-6/+6
Most device tree files already do this, so update the remaining ones for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove spurious tabsThierry Reding1-12/+12
Remove tabs in places where they don't belong (i.e. where a single space is sufficient). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Populate VBUS for USB3 on Jetson TX2Jon Hunter1-0/+1
The VBUS for USB3 connector on the Jetson TX2 is connected to the vdd_usb1 supply and although this is populated for the USB2 port on the USB3 connector it is not populated for the USB3 port and causes the following warning to be seen on boot ... usb3-0: supply vbus not found, using dummy regulator Fix this by also adding the VBUS supply to the USB3 port. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Enable DFLL support on Jetson NanoJon Hunter1-0/+37
Populate the DFLL node and corresponding PWM pin nodes in order to enable CPUFREQ support on the Jetson Nano platform. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Add support for Jetson Xavier NXJon Hunter3-0/+622
Add the device-tree source files for the Tegra194 Jetson Xavier NX Developer Kit. The Xavier NX Developer Kit consists of a small form factor system-on-module (SOM) board (part number p3668-0000) and a carrier board (part number p3509-0000). The Xavier NX Developer Kit SOM features a micro-SD card slot, however, there is also a variant of the SOM available that features a 16GB eMMC. Given that the carrier board can be used with the different SOM variants, that have different part numbers, both the compatible string and file name of the device-tree source file for the Developer Kit is a concatenation of the SOM and carrier board part numbers. Based on some initial work by Thierry Reding <treding@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Re-order PCIe aperture mappingsVidya Sagar1-18/+18
Re-order Tegra194's PCIe aperture mappings to have IO window moved to 64-bit aperture and have the entire 32-bit aperture used for accessing the configuration space. This makes it to use the entire 32MB of the 32-bit aperture for ECAM purpose while booting through ACPI. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Enable Tegra VI CSI support for Jetson NanoSowjanya Komatineni1-0/+10
This patch enables VI and CSI in device tree for Jetson Nano. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: jetson-tx1: Add camera suppliesSowjanya Komatineni1-0/+38
Jetson TX1 development board has a camera expansion connector which has 2V8, 1V8 and 1V2 supplies to power up the camera sensor on the supported camera modules. Camera module designed as per Jetson TX1 camera expansion connector may use these supplies for camera sensor avdd 2V8, digital core 1V8, and digital interface 1V2 voltages. These supplies are from fixed regulators on TX1 carrier board with enable control signals from I2C GPIO expanders. This patch adds these camera supplies to Jetson TX1 device tree to allow using these when a camera module is used. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix order of XUSB controller clocksThierry Reding1-2/+2
This is purely to make the json-schema validation tools happy because they cannot deal with string arrays that may be in arbitrary order. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Rename cbb@0 to bus@0 on Tegra194Thierry Reding3-17/+17
The control backbone is a simple-bus and hence its device tree node should be named "bus@<unit-address>" according to the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Sort nodes by unit-address on Jetson NanoThierry Reding1-8/+8
Move the usb@700d0000 node to the correct place in the device tree, ordered by unit-address. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Various fixes for PMICsThierry Reding2-26/+25
Standardize on "pmic" as the node name for the PMIC on Tegra210 systems and use consistent names for pinmux and GPIO hog nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Rename agic -> interrupt-controllerThierry Reding3-3/+3
Device tree nodes for interrupt controllers should be named "interrupt- controller", so rename the AGIC accordingly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix indentation in Tegra194 device treeThierry Reding1-1/+1
Properly indent subsequent lines so that they align with the first line. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix indentation in Tegra132 device treeThierry Reding1-1/+1
Properly indent subsequent lines so that they align with the first line. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove unused interrupts from Tegra194 AON GPIOThierry Reding1-4/+1
The AON GPIO controller on Tegra194 currently only uses a single interrupt, so remove the extra ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use standard names for SRAM nodesThierry Reding2-10/+6
SRAM nodes should be named sram@<unit-address> to match the bindings. While at it, also remove the unneeded, custom compatible string for SRAM partition nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark display hub as simple busThierry Reding2-2/+2
The display hub on Tegra186 and Tegra194 is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix {clock,reset}-names orderingThierry Reding1-6/+6
It's very difficult to describe string lists that can be in arbitrary order using the json-schema based validation tooling. Since the OS is not going to care either way, take the easy way out and reorder these entries to match the order defined in the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove XUSB pad controller interrupt from XUSB nodeThierry Reding2-4/+2
The XUSB controller doesn't need the XUSB pad controller's interrupt, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use standard EEPROM propertiesThierry Reding5-12/+12
The address-bits and page-size properties that are currently used are not valid properties according to the bindings. Use the address-width and pagesize properties instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-05 06:34:35 +0300