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2020-11-25arm64: tegra: Wrong AON HSP reg property sizeDipen Patel1-1/+1
The AON HSP node's "reg" property size 0xa0000 will overlap with other resources. This patch fixes that wrong value with correct size 0x90000. Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Dipen Patel <dipenp@nvidia.com> Fixes: a38570c22e9d ("arm64: tegra: Add nodes for TCU on Tegra194") Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-10-24Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-5/+242
Pull ARM Devicetree updates from Olof Johansson: "As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits) ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users arm64: dts: lg: Fix SP805 clocks ARM: mstar: Fix up the fallout from moving the dts/dtsi files ARM: mstar: Add mstar prefix to all of the dtsi/dts files ARM: mstar: Add interrupt to pm_uart ARM: mstar: Add interrupt controller to base dtsi ARM: dts: meson8: remove two invalid interrupt lines from the GPU node arm64: dts: ti: k3-j7200-common-proc-board: Add USB support arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function arm64: dts: ti: k3-j7200-main: Add USB controller arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC ARM: dts: hisilicon: add SD5203 dts ARM: dts: hisilicon: fix the system controller compatible nodes arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 arm64: dts: zynqmp: Remove undocumented u-boot properties arm64: dts: zynqmp: Remove additional compatible string for i2c IPs arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml ...
2020-09-02arm64: tegra: Add DT binding for AHUB componentsSameer Pujar1-1/+224
This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194. Bindings for following modules are added. * AHUB added as a child node under ACONNECT * AHUB includes many HW accelerators and below components are added as its children. * ADMAIF * I2S * DMIC * DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does not have this module) Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-28arm64: tegra: Add missing timeout clock to Tegra194 SDMMC nodesSowjanya Komatineni1-6/+9
commit 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree") Tegra194 uses separate SDMMC_LEGACY_TM clock for data timeout and this clock is not enabled currently which is not recommended. Tegra194 SDMMC advertises 12Mhz as timeout clock frequency in host capability register. So, this clock should be kept enabled by SDMMC driver. Fixes: 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-7-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-08-27arm64: tegra: Properly size register regions for GPU on Tegra194Thierry Reding1-2/+2
Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather than 256 MiB. Reported-by: Terje Bergström <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-By: Terje Bergström <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-08-27arm64: tegra: Wire up pinctrl states for all DPAUX controllersThierry Reding1-2/+16
All four DPAUX controllers on Tegra194 control the pin configuration of their companion I2C controllers. Wire up all the pinctrl states for the I2C controllers so that their pins can be correctly muxed when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-17arm64: tegra: Add the GPU on Tegra194Thierry Reding1-0/+34
The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called GV11B. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-16arm64: tegra: Add compatible string for Tegra194 CPU complexSumit Gupta1-0/+2
On Tegra194, data on valid operating points for the CPUs needs to be queried from BPMP. However, there is no node representing CPU complex. So, add a compatible string to the 'cpus' node instead of using dummy node to bind the cpufreq driver to. Also, add reference to the BPMP instance for the CPU complex. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove spurious tabsThierry Reding1-12/+12
Remove tabs in places where they don't belong (i.e. where a single space is sufficient). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Re-order PCIe aperture mappingsVidya Sagar1-18/+18
Re-order Tegra194's PCIe aperture mappings to have IO window moved to 64-bit aperture and have the entire 32-bit aperture used for accessing the configuration space. This makes it to use the entire 32MB of the 32-bit aperture for ECAM purpose while booting through ACPI. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Rename cbb@0 to bus@0 on Tegra194Thierry Reding1-1/+1
The control backbone is a simple-bus and hence its device tree node should be named "bus@<unit-address>" according to the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Fix indentation in Tegra194 device treeThierry Reding1-1/+1
Properly indent subsequent lines so that they align with the first line. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove unused interrupts from Tegra194 AON GPIOThierry Reding1-4/+1
The AON GPIO controller on Tegra194 currently only uses a single interrupt, so remove the extra ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use standard names for SRAM nodesThierry Reding1-5/+3
SRAM nodes should be named sram@<unit-address> to match the bindings. While at it, also remove the unneeded, custom compatible string for SRAM partition nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark display hub as simple busThierry Reding1-1/+1
The display hub on Tegra186 and Tegra194 is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Remove XUSB pad controller interrupt from XUSB nodeThierry Reding1-2/+1
The XUSB controller doesn't need the XUSB pad controller's interrupt, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Do not mark host1x as simple busThierry Reding1-1/+1
The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-15arm64: tegra: Use proper tuple notationThierry Reding1-56/+56
Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Rename sdhci nodes to mmcThierry Reding1-3/+3
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt-names for host1xThierry Reding1-0/+1
Interrupt names are used to distinguish between the syncpoint and general host1x interrupts. Make sure they are available in the DT so that drivers can use them if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Add interrupt for Tegra194 memory controllerThierry Reding1-0/+1
This interrupt can be used for the operating system to be interrupted when certain events occur. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Describe interconnect paths on Tegra194Thierry Reding1-0/+70
On Tegra194, all clients of the memory subsystem can generally address 40 bits of system memory. However, bit 39 has special meaning and will cause the memory controller to reorder sectors for block-linear buffer formats. This is primarily useful for graphics-related devices. Use of bit 39 must be controlled on a case-by-case basis. Buffers that are used with bit 39 set by one device may be used with bit 39 cleared by other devices. Care must be taken to allocate buffers at addresses that do not require bit 39 to be set. This is normally not an issue for system memory since there are no Tegra-based systems with enough RAM to exhaust the 39-bit physical address space. However, when a device is behind an IOMMU, such as the ARM SMMU on Tegra194, the IOMMUs input address space can cause IOVA allocations to happen in this region. This is for example the case when an operating system implements a top-down allocation policy for IO virtual addresses. To account for this, describe the path that memory accesses take through the system. Memory clients will send requests to the memory controller, which forwards bits [38:0] of the address either to the external memory controller or the SMMU, depending on the stream ID of the access. A good way to describe this is using the interconnects bindings, see: Documentation/devicetree/bindings/interconnect/interconnect.txt The standard "dma-mem" path is used to describe the path towards system memory via the memory controller. A dma-ranges property in the memory controller's device tree node limits the range of DMA addresses that the memory clients can use to bits [38:0], ensuring that bit 39 is not used. Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v4: - add additional entries for interconnect-names to match interconnects - add EMC as destination for interconnect paths Changes in v3: - add missing interconnect properties for VIC Changes in v2: - use memory client IDs instead of stream IDs (Mikko Perttunen) Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-23arm64: tegra: Remove extra compatible for Tegra194 SDHCIThierry Reding1-3/+3
The SDHCI on Tegra194 is in fact not compatible with the one found on Tegra186. Remove the extra compatible string to reflect that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-20arm64: tegra: Fix flag for 64-bit resources in 'ranges' propertyVidya Sagar1-6/+6
Fix flag in PCIe controllers device-tree nodes 'ranges' property to correctly represent 64-bit resources. Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-13arm64: tegra: Add XUDC node on Tegra194Nagarjuna Kristam1-0/+18
Tegra194 has one XUSB device mode controller which can be operated in HS and SS modes. Add a DT node for this XUSB device mode controller. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194Vidya Sagar1-0/+99
Add endpoint mode controllers nodes for the dual mode PCIe controllers present in Tegra194 SoC. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Add XUSB and pad controller on Tegra194JC Kuo1-0/+139
Adds the XUSB pad and XUSB controllers on Tegra194. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12arm64: tegra: Fix Tegra194 PCIe compatible stringJon Hunter1-6/+6
If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled then this can cause the kernel to incorrectly probe the generic designware PCIe platform driver instead of the Tegra194 designware PCIe driver. This causes a boot failure on Tegra194 because the necessary configuration to access the hardware is not performed. The order in which the compatible strings are populated in Device-Tree is not relevant in this case, because the kernel will attempt to probe the device as soon as a driver is loaded and if the generic designware PCIe driver is loaded first, then this driver will be probed first. Therefore, to fix this problem, remove the "snps,dw-pcie" string from the compatible string as we never want this driver to be probe on Tegra194. Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09arm64: tegra: Add fuse/apbmisc node on Tegra194JC Kuo1-0/+13
This commit adds Tegra194 fuse and apbmisc device nodes. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09arm64: tegra: Add the memory subsystem on Tegra194Thierry Reding1-0/+43
The memory subsystem on Tegra194 encompasses both the memory and external memory controllers. The EMC is represented as a subnode of the MC and a ranges property is used to describe the register ranges. A dma-ranges property is also added to describe that all memory clients can address up to 39 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. A memory client can technically use 40 bits of addresses, but the memory controller on Tegra194 uses bit 39 to determine the XBAR format used to access memory. Use of this bit needs to be explicitly controlled by the operating system drivers for devices that can use this on-the-fly format conversion. Using the dma-ranges property prevents the operating system from using the bit implicitly, for example in I/O virtual address mappings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Assume no CLKREQ presence by defaultVidya Sagar1-6/+0
Although Tegra194 has support for CLKREQ sideband signal and P2972 has routing of the same till the slot, it is the case most of the time that the connected device doesn't have CLKREQ support. Hence, it makes sense to assume that there is no CLKREQ support by default and it can be enabled on need basis when a card with CLKREQ support is connected. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix compatible string for EQOS on Tegra194Thierry Reding1-1/+2
The EQOS Ethernet controller found on Tegra194 is compatible with its predecessor or Tegra186. However, it is an established practice to add a compatible string for the most recent generation of the SoC as well, just in case some incompatibilities or bugs are later discovered. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Fix base address for SOR1 on Tegra194Thierry Reding1-1/+1
The SOR1 hardware block's registers start at physical address 0x15b40000 as correctly specified by the unit-address, but the reg property lists a wrong value, likely because it was copy-and-pasted from SOR0 but not correctly updated. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add unit-address for ACONNECT on Tegra194Thierry Reding1-1/+1
The ACONNECT complex starts at physical address 0x2900000, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add unit-address for CBB on Tegra194Thierry Reding1-1/+1
The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29arm64: tegra: Add CPU and cache topology for Tegra194Thierry Reding1-12/+144
Tegra194 has four CPU clusters, each with their own cache hierarchy. This patch creates the CPU map for these clusters and adds the second- and third-level caches and associates them with the CPUs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-09-20arm64: tegra: Add configuration for PCIe C5 sideband signalsVidya Sagar1-1/+37
Add support to configure PCIe C5's sideband signals PERST# and CLKREQ# as output and bi-directional signals respectively which unlike other PCIe controllers sideband signals are not configured by default. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2019-06-21arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DTVidya Sagar1-0/+437
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree. The Tegra194 SoC contains six PCIe controllers and twenty P2U instances grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us) and NVIDIA High Speed (NVHS-8 P2Us) respectively. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-21arm64: tegra: Add ACONNECT, ADMA and AGIC nodesSameer Pujar1-0/+71
Add device tree nodes for the ACONNECT, ADMA and AGIC devices on Tegra186 and Tegra194. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-14arm64: tegra: Mark architected timer as always onThierry Reding1-0/+1
The architected timer on Tegra186 and Tegra194 is in an always on power partition and its reference clock will always run, so mark the timer as always on. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-15Merge tag 'tegra-for-5.1-arm64-dt' of ↵Arnd Bergmann1-3/+74
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.1-rc1 This contains a couple of fixes to existing device trees, enables CPU frequency scaling on various Tegra210 boards, enables the TCU as debug serial port on Jetson Xavier, adds various improvements for SDMMC on Tegra210, Tegra186 and Tegra194 boards and finally adds initial support for the NVIDIA Shield TV. * tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits) arm64: tegra: Update compatible for Tegra186 I2C arm64: tegra: Update compatible for Tegra210 I2C arm64: tegra: Support 200 MHz for SDMMC on Tegra194 arm64: tegra: Add CQE Support for SDMMC4 arm64: tegra: Add SDMMC auto-calibration settings arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888 arm64: tegra: Add nodes for TCU on Tegra194 arm64: tegra: Enable DFLL clock on Smaug arm64: tegra: Add CPU power rail regulator on Smaug arm64: tegra: Enable DFLL clock on Jetson TX1 arm64: tegra: Add pinmux for PWM-based DFLL support on P2597 arm64: tegra: Add CPU clocks on Tegra210 arm64: tegra: Add DFLL clock on Tegra210 arm64: tegra: p2771-0000: Use TEGRA186_ prefix for GPIO names arm64: tegra: p3310: Use TEGRA186_ prefix for GPIO names arm64: tegra: p2597: Sort nodes by unit-address arm64: tegra: p2972: Sort nodes properly arm64: tegra: Add regulators for Tegra210 Darcy arm64: tegra: Add pinmux for Darcy board arm64: tegra: Add gpio-keys nodes for Darcy ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-07arm64: tegra: Support 200 MHz for SDMMC on Tegra194Sowjanya Komatineni1-0/+4
Change the SDMMC clock source to support a maximum frequency of 200 MHz on Tegra194. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add CQE Support for SDMMC4Sowjanya Komatineni1-0/+1
Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add SDMMC auto-calibration settingsSowjanya Komatineni1-0/+34
Add SDMMC initial pad offsets used by auto calibration process. Add SDMMC fixed drive strengths for Tegra210, Tegra186 and Tegra194 which are used when calibration timeouts. Fixed drive strengths are based on Pre SI Analysis of the pads. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add nodes for TCU on Tegra194Mikko Perttunen1-3/+35
Add nodes required for communication through the Tegra Combined UART. This includes the AON HSP instance, addition of shared interrupts for the TOP0 HSP instance, and finally the TCU node itself. Also mark the HSP instances as compatible to tegra194-hsp, as the hardware is not identical but is compatible to tegra186-hsp. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-30arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring1-8/+8
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-12-07arm64: tegra: Set reg property for display-hub on Tegra194Thierry Reding1-0/+1
Technically the display-hub driver could access registers via the specified region, though it practice it will do so via the display controllers' register regions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06arm64: tegra: Add CEC controller on Tegra194Thierry Reding1-0/+9
The CEC controller found on Tegra194 can be used to control consumer devices using the HDMI CEC pin. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-06arm64: tegra: Add HDA controller on Tegra194Sameer Pujar1-0/+16
The HDA controller found on Tegra194 can be used for audio playback over HDMI. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Add AON GPIO controller on Tegra194Thierry Reding1-0/+15
The AON GPIO controller is in an always-on power partition and typically provides pins for functions that need to always work, such as the power key for example. Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-03 00:43:59 +0300