summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/marvell/cn9130.dtsi
AgeCommit message (Collapse)AuthorFilesLines
2021-12-17arm64: dts: marvell: cn9130: enable CP0 GPIO controllersRobert Marko1-0/+8
CN9130 has a built-in CP115 which has 2 GPIO controllers, but unlike in Armada 7k and 8k both are left disabled by the SoC DTSI. This first of all makes no sense as they are always present due to being SoC built-in and its an issue as boards like CN9130-CRB use the CPO GPIO2 pins for regulators and SD card support without enabling them first. So, enable both of them like Armada 7k and 8k do. Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-12-17arm64: dts: marvell: cn9130: add GPIO and SPI aliasesRobert Marko1-0/+7
CN9130 has one CP115 built in, which like the CP110 has 2 GPIO and 2 SPI controllers built-in. However, unlike the Armada 7k and 8k the SoC DTSI doesn't add the required aliases as both the Orion SPI driver and MVEBU GPIO drivers require the aliases to be present. So add the required aliases for GPIO and SPI controllers. Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-10-09arm64: dts: marvell: Add support for Marvell CN9130 SoC supportMiquel Raynal1-0/+37
A CN9130 SoC has one AP807 and one internal CP115. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>