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2022-03-16arm64: dts: marvell: armada-37xx: Remap IO space to bus address 0x0Pali Rohár1-1/+1
commit a1cc1697bb56cdf880ad4d17b79a39ef2c294bc9 upstream. Legacy and old PCI I/O based cards do not support 32-bit I/O addressing. Since commit 64f160e19e92 ("PCI: aardvark: Configure PCIe resources from 'ranges' DT property") kernel can set different PCIe address on CPU and different on the bus for the one A37xx address mapping without any firmware support in case the bus address does not conflict with other A37xx mapping. So remap I/O space to the bus address 0x0 to enable support for old legacy I/O port based cards which have hardcoded I/O ports in low address space. Note that DDR on A37xx is mapped to bus address 0x0. And mapping of I/O space can be set to address 0x0 too because MEM space and I/O space are separate and so do not conflict. Remapping IO space on Turris Mox to different address is not possible to due bootloader bug. Signed-off-by: Pali Rohár <pali@kernel.org> Reported-by: Arnd Bergmann <arnd@arndb.de> Fixes: 76f6386b25cc ("arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700") Cc: stable@vger.kernel.org # 64f160e19e92 ("PCI: aardvark: Configure PCIe resources from 'ranges' DT property") Cc: stable@vger.kernel.org # 514ef1e62d65 ("arm64: dts: marvell: armada-37xx: Extend PCIe MEM space") Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-08-17arm64: dts: marvell: armada-37xx: Extend PCIe MEM spacePali Rohár1-2/+9
Current PCIe MEM space of size 16 MB is not enough for some combination of PCIe cards (e.g. NVMe disk together with ath11k wifi card). ARM Trusted Firmware for Armada 3700 platform already assigns 128 MB for PCIe window, so extend PCIe MEM space to the end of 128 MB PCIe window which allows to allocate more PCIe BARs for more PCIe cards. Without this change some combination of PCIe cards cannot be used and kernel show error messages in dmesg during initialization: pci 0000:00:00.0: BAR 8: no space for [mem size 0x01800000] pci 0000:00:00.0: BAR 8: failed to assign [mem size 0x01800000] pci 0000:00:00.0: BAR 6: assigned [mem 0xe8000000-0xe80007ff pref] pci 0000:01:00.0: BAR 8: no space for [mem size 0x01800000] pci 0000:01:00.0: BAR 8: failed to assign [mem size 0x01800000] pci 0000:02:03.0: BAR 8: no space for [mem size 0x01000000] pci 0000:02:03.0: BAR 8: failed to assign [mem size 0x01000000] pci 0000:02:07.0: BAR 8: no space for [mem size 0x00100000] pci 0000:02:07.0: BAR 8: failed to assign [mem size 0x00100000] pci 0000:03:00.0: BAR 0: no space for [mem size 0x01000000 64bit] pci 0000:03:00.0: BAR 0: failed to assign [mem size 0x01000000 64bit] Due to bugs in U-Boot port for Turris Mox, the second range in Turris Mox kernel DTS file for PCIe must start at 16 MB offset. Otherwise U-Boot crashes during loading of kernel DTB file. This bug is present only in U-Boot code for Turris Mox and therefore other Armada 3700 devices are not affected by this bug. Bug is fixed in U-Boot version 2021.07. To not break booting new kernels on existing versions of U-Boot on Turris Mox, use first 16 MB range for IO and second range with rest of PCIe window for MEM. Signed-off-by: Pali Rohár <pali@kernel.org> Fixes: 76f6386b25cc ("arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700") Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-07-10Merge tag 'arm-dt-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+8
Pull ARM devicetree updates from Olof Johansson: "Like always, the DT branch is sizable. There are numerous additions and fixes to existing platforms, but also a handful of new ones introduced. Less than some other releases, but there's been significant work on cleanups, refactorings and device enabling on existing platforms. A non-exhaustive list of new material: - Refactoring of BCM2711 dtsi structure to add support for the Raspberry Pi 400 - Rockchip: RK3568 SoC and EVB, video codecs for rk3036/3066/3188/322x - Qualcomm: SA8155p Automotive platform (SM8150 derivative), SM8150/8250 enhancements and support for Sony Xperia 1/1II and 5/5II - TI K3: PCI/USB3 support on AM64-sk boards, R5 remoteproc definitions - TI OMAP: Various cleanups - Tegra: Audio support for Jetson Xavier NX, SMMU support on Tegra194 - Qualcomm: lots of additions for peripherals across several SoCs, and new support for Microsoft Surface Duo (SM8150-based), Huawei Ascend G7. - i.MX: Numerous additions of features across SoCs and boards. - Allwinner: More device bindings for V3s, Forlinx OKA40i-C and NanoPi R1S H5 boards - MediaTek: More device bindings for mt8167, new Chromebook system variants for mt8183 - Renesas: RZ/G2L SoC and EVK added - Amlogic: BananaPi BPI-M5 board added" * tag 'arm-dt-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (511 commits) arm64: dts: rockchip: add basic dts for RK3568 EVB arm64: dts: rockchip: add core dtsi for RK3568 SoC arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs ARM: dts: rockchip: add vpu and vdec node for RK322x ARM: dts: rockchip: add vpu nodes for RK3066 and RK3188 ARM: dts: rockchip: add vpu node for RK3036 arm64: dts: ipq8074: Add QUP6 I2C node arm64: dts: rockchip: Re-add regulator-always-on for vcc_sdio for rk3399-roc-pc arm64: dts: rockchip: Re-add regulator-boot-on, regulator-always-on for vdd_gpu on rk3399-roc-pc arm64: dts: rockchip: add ir-receiver for rk3399-roc-pc arm64: dts: rockchip: Add USB-C port details for rk3399 Firefly arm64: dts: rockchip: Sort rk3399 firefly pinmux entries arm64: dts: rockchip: add infrared receiver node to RK3399 Firefly arm64: dts: rockchip: add SPDIF node for rk3399-firefly arm64: dts: rockchip: Add Rotation Property for OGA Panel arm64: dts: qcom: sc7180: bus votes for eMMC and SD card arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen arm64: dts: qcom: sm8250-edo: Enable GPI DMA arm64: dts: qcom: sm8250-edo: Enable ADSP/CDSP/SLPI arm64: dts: qcom: sm8250-edo: Enable PCIe ...
2021-06-25arm64: dts: marvell: armada-37xx: Fix reg for standard variant of UARTPali Rohár1-1/+1
UART1 (standard variant with DT node name 'uart0') has register space 0x12000-0x12018 and not whole size 0x200. So fix also this in example. Signed-off-by: Pali Rohár <pali@kernel.org> Fixes: c737abc193d1 ("arm64: dts: marvell: Fix A37xx UART0 register size") Link: https://lore.kernel.org/r/20210624224909.6350-6-pali@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-17arm64: dts: marvell: armada-37xx: move firmware node to generic dtsi filePali Rohár1-0/+8
Move the turris-mox-rwtm firmware node from Turris MOX' device tree into the generic armada-37xx.dtsi file and use the generic compatible string 'marvell,armada-3700-rwtm-firmware' instead of the current one. Turris MOX DTS file contains also old compatible string for backward compatibility. The Turris MOX rWTM firmware can be used on any Armada 37xx device, giving them access to the rWTM hardware random number generator, which is otherwise unavailable. This change allows Linux to load the turris-mox-rwtm.ko module on these boards. Tested on ESPRESSObin v5 with both default Marvell WTMI firmware and CZ.NIC's firmware. With default WTMI firmware the turris-mox-rwtm fails to probe, while with CZ.NIC's firmware it registers the HW random number generator. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-04-02arm64: dts: marvell: armada-37xx: add syscon compatible to NB clk nodeMarek Behún1-1/+2
Add "syscon" compatible to the North Bridge clocks node to allow the cpufreq driver to access these registers via syscon API. This is needed for a fix of cpufreq driver. Signed-off-by: Marek Behún <kabel@kernel.org> Fixes: e8d66e7927b2 ("arm64: dts: marvell: armada-37xx: add nodes...") Cc: stable@vger.kernel.org Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-01-29arm64: dts: marvell: armada-37xx: Add SATA comphy into main armada-37xx.dtsi ↵Pali Rohár1-0/+2
file SATA on A3720 SOC can use only comphy2, so move this definition from board specific DTS file armada-3720-espressobin.dtsi into main A3720 SOC file armada-37xx.dtsi. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-08-27pinctrl: armada-37xx: Add comment for pcie1_reset pin groupPali Rohár1-1/+1
Group name 'pcie1' is misleading as it controls only PCIe reset pin. Like other PCIe groups it should have been called 'pcie1_reset'. But due to backward compatibility it is not possible to change existing group name. So just add comment describing this PCIe reset functionality. Signed-off-by: Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20200724132457.7094-1-pali@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-05-17arm64: dts: marvell: armada-37xx: Move PCIe max-link-speed propertyPali Rohár1-0/+1
Move the max-link-speed property of the PCIe node from board specific device tree files to the generic armada-37xx.dtsi. Armada 37xx supports only PCIe gen2 speed so max-link-speed property should be in the generic armada-37xx.dtsi file. Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-05-17arm64: dts: marvell: armada-37xx: Move PCIe comphy handle propertyMarek Behún1-0/+1
Move the comphy handle property of the PCIe node from board specific device tree files (EspressoBin and Turris Mox) to the generic armada-37xx.dtsi. This is correct since this is the only possible PCIe PHY configuration on Armada 37xx, so when PCIe is enabled on any board, this handle is correct. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-05-17arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio functionMarek Behún1-1/+1
We found out that we are unable to control the PERST# signal via the default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe register space called PERSTN_GPIO_EN (D0088004[3]), but changing the value of this register does not change the pin output when measuring with voltmeter. We do not know if this is a bug in the SOC, or if it works only when PCIe controller is in a certain state. Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before training link") says that when this pin changes pinctrl mode from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief moment. So currently the situation is that on A3700 boards the PERST# signal is asserted in U-Boot (because the code in U-Boot issues reset via this pin via GPIO mode), and then in Linux by the obscure and undocumented mechanism described by the above mentioned commit. We want to issue PERST# signal in a known way, therefore this patch changes the pcie_reset_pin function from "pcie" to "gpio" and adds the reset-gpios property to the PCIe node in device tree files of EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already has this property and uDPU does not have a PCIe port). Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Remi Pommarel <repk@triplefau.lt> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-31arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrlMarek Behún1-0/+5
This adds pinctrl node for the GPIO to be used as SPI chip select 1. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-08-27arm64: dts: marvell: armada-37xx: add mailbox nodeMarek Behún1-0/+7
This adds the rWTM BIU mailbox node for communication with the secure processor. The driver already exists in drivers/mailbox/armada-37xx-rwtm-mailbox.c. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-15Merge tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu into arm/dtArnd Bergmann1-2/+78
mvebu dt64 for 5.1 (part 1) - Interrupt support to Armada 7K/8K thermal nodes - Armada 37xx related patches allowing to enable suspend to RAM (USB2, USB3, PCIe, SATA, DSA) - uDPU board support (Armada-3720 based):single-port FTTdp distribution point unit - Fixes for EspressoBin Ethernet support when using U-Boot mainline - cleanup for partitions under flashes nodes * tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY property arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHY arm64: dts: marvell: armada-37xx: declare the COMPHY node arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashes arm64: dts: armada-3720-espressobin: Set mv88e6341 cpu port as RGMII-ID arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pins arm64: dts: marvell: Add device tree for uDPU board arm64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pin arm64: dts: marvell: armada-37xx: declare PCIe reset pin arm64: dts: marvell: armada-37xx: declare USB2 UTMI PHYs arm64: dts: marvell: armada-37xx: fix USB2 memory region arm64: dts: marvell: armada-37xx: declare SATA clock arm64: dts: marvell: armada-37xx: fix SATA node scope arm64: dts: marvell: add interrupt support to cp110 thermal node arm64: dts: marvell: add interrupt support to ap806 thermal node Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-08arm64: dts: marvell: armada-37xx: link USB hosts with their PHYsMiquel Raynal1-0/+4
Reference the PHY nodes from the USB controller nodes. The USB3 host controller is wired to: * the first PHY of the COMPHY IP * the OTG-capable UTMI PHY The USB2 host controller is wired to: * the host-only UTMI PHY Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: marvell: armada-37xx: declare the COMPHY nodeMiquel Raynal1-0/+29
Describe the A3700 COMPHY node. It has three PHYs that can be configured as follow: * PCIe or GbE * USB3 or GbE * SATA or USB3 Each of them has its own memory area. Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pinsRemi Pommarel1-0/+5
In order to be able to communicate with the 88e6341 switch some pins have to be repurposed as RGMII and SMI pins. This fixes ethernet support on system booted via a bootloader that has not already configured those pins (e.g. mainline u-boot, or vendor u-boot compiled without ethernet support). Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: declare PCIe reset pinMiquel Raynal1-0/+9
One pin can be muxed as PCIe endpoint card reset. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: declare USB2 UTMI PHYsMiquel Raynal1-0/+28
On Marvell Armada 3700 SoCs there are two USB2 UTMI PHYs. They are both very similar but only one has OTG/charging capabilities. Because there are USB host registers and PHY registers mixed in a single area, a system controller is also created and referenced from both the USB host node and the PHY node. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: fix USB2 memory regionMiquel Raynal1-1/+1
The specification splits the USB2 memory region into three sections: 1/ 0xD005E000-0xD005EFFF: USB2 Host Controller Registers 2/ 0xD005F000-0xD005F7FF: USB2 UTMI PHY Registers 3/ 0xD005F800-0xD005FFFF: USB2 Host Miscellaneous Registers Section 1/ belongs to the USB2 node but section 2/ belongs to the UTMI PHY node. Section 3/ can be accessed by both the USB controller and the PHY because of the miscaellaneous nature of the registers inside so a specific node will be created to cover the area and a handle to it will be added in both the USB controller and the PHY node. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: declare SATA clockMiquel Raynal1-0/+1
The SATA IP get its clock from the north-bridge. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: fix SATA node scopeMiquel Raynal1-1/+1
Fix the SATA IP memory area which is only 0x178 bytes long (from Marvell A3700 specification). Actually, starting from the offset 0xe0178, there is an area dedicated to the COMPHY driver. Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-01-30arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring1-1/+1
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-11-30arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl definitionDing Tao1-0/+10
Add emmc/sdio pinctrl definition for marvell armada37xx SoCs. Signed-off-by: Ding Tao <miyatsu@qq.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-02arm64: dts: marvell: Add node labels for the cpusGregory CLEMENT1-1/+1
Aligned with what we have done for the others nodes. It will also allow to easily modify the cpu configuration at board (or sub-SoC) level. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-28arm64: dts: marvell: armada-37xx: add nodes to support watchdogMarek Behún1-0/+13
This adds the system controller node for CPU Miscellaneous Registers (which is needed for the watchdog node) and the watchdog node. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-07-13arm64: dts: marvell: armada-37xx: update the crypto engine compatibleAntoine Tenart1-1/+1
New compatibles are now supported by the Inside Secure SafeXcel driver. As they are more specific than the old ones, they should be used whenever possible. This patch updates the Marvell Armada 37xx device tree accordingly. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-06-29arm64: dts: marvell: armada-37xx: reserve memory for ATFVictor Gu1-0/+15
The PSCI area should be reserved in Linux for PSCI operations such as suspend/resume. Reserve 2MiB of memory which matches the area used by ATF (BL1, BL2, BL3x, see [1] in ATF source code). This covers all PSCI code and data area and is 2MiB aligned, which is required by Linux for huge pages handling. Please note that this is a default setup allowing to perform PSCI operations with legacy bootloaders. Recent bootloaders should update the region size/position accordingly. [1] plat/marvell/a3700/common/include/platform_def.h Signed-off-by: Victor Gu <xigu@marvell.com> [miquel.raynal@bootlin.com: reword of commit message, comment in the DTSI] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-06-29arm64: dts: marvell: armada-37xx: add the node allowing AVS supportGregory CLEMENT1-0/+6
In order to be able to use Adaptive Voltage Scaling, we need to add a reference to these registers. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-05-18arm64: dts: marvell: armada-37xx: mark the gpio controllers as irq controllerUwe Kleine-König1-0/+6
This allows to reference these gpio controller as interrupt parent. Also add a comment which cpu line names are managed by the controllers because "nb" and "sb" usually doesn't appear in schematics, but MPPX_Y do. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-02-14arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCsGregory CLEMENT1-37/+1
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-01-05arm64: dts: marvell: armada-37xx: add a crypto nodeAntoine Tenart1-0/+14
This patch adds a crypto node describing the EIP97 engine found in Armada 37xx SoCs. The cryptographic engine is enabled by default. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-12-18arm64: dts: marvell: armada-37xx: add nodes allowing cpufreq supportGregory CLEMENT1-0/+7
In order to be able to use cpu freq, we need to associate a clock to each CPU and to expose the power management registers. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-10-30arm64: dts: marvell: armada-37xx: add second UART portMiquel Raynal1-1/+17
Add a node in Armada 37xx DTSI file for the second UART, with a different compatible due to its extended IP which has some differences with the first UART already in place. Make use of this commit to also fully describe the first port and use the same clear and named interrupt bindings for both ports. The standard UART (UART0) uses level-interrupts while the extended UART (UART1) uses edge-triggered interrupts. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-10-30arm64: dts: marvell: armada-37xx: add UART clockMiquel Raynal1-0/+1
Add the missing clock property to armada-3700 UART node. This clock will be used to derive the prescaler value to comply with the requested baudrate. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-09-20arm64: dts: marvell: 37xx: remove empty lineAntoine Tenart1-1/+0
Cosmetic patch removing an empty line at the end of the NB pinctrl node. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-09-19arm64: dts: marvell: Fix A37xx UART0 register sizeallen yan1-1/+1
Armada-37xx UART0 registers are 0x200 bytes wide. Right next to them are the UART1 registers that should not be declared in this node. Update the example in DT bindings document accordingly. Signed-off-by: allen yan <yanwei@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-08-02ARM64: dts: marvell: armada-37xx: Wire PMUv3Marc Zyngier1-0/+5
The Cortex-A53s that power the Armada-37xx SoCs are equipped with a PMUv3, just like most ARMv8 cores. Advertise the PMUv3 presence in the device tree, and wire its interrupt. This allows the perf subsystem to work correctly. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-08-02ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interfaceMarc Zyngier1-1/+4
The Cortex-A53s that power the Armada-37xx SoCs are equipped with a GIC CPU interface that gets enabled when coupled with a GICv3 interrupt controller, such as the GIC-500 on the this SoC. Advertise the MMIO ranges provided by the CPUs, which enables (among other things) GICv2 guests to run under a hypervisor such as KVM. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-08-02ARM64: dts: marvell: armada-37xx: Fix GIC maintenance interruptMarc Zyngier1-0/+1
The GIC-500 integrated in the Armada-37xx SoCs is compliant with the GICv3 architecture, and thus provides a maintenance interrupt that is required for hypervisors to function correctly. With the interrupt provided in the DT, KVM now works as it should. Tested on an Espressobin system. Fixes: adbc3695d9e4 ("arm64: dts: add the Marvell Armada 3700 family and a development board") Cc: <stable@vger.kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-08-02ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridgeGregory CLEMENT1-1/+1
The number of pins in South Bridge is 30 and not 29. There is a fix for the driver for the pinctrl, but a fix is also need at device tree level for the GPIO. Fixes: afda007feda5 ("ARM64: dts: marvell: Add pinctrl nodes for Armada 3700") Cc: <stable@vger.kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-07-03ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiersMarc Zyngier1-8/+4
Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult. Fixes: adbc3695d9e4 ("arm64: dts: add the Marvell Armada 3700 family and a development board") Cc: <stable@vger.kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-17arm64: dts: marvell: Enable second SDHCI controller in Armada 37xxKonstantin Porotchkin1-0/+11
The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second one. Moreover, the Armada 37xx DB v2 board populates the 2 SDHCI interfaces. The second interface is using pluggable module that can either have an SD connector or eMMC on it. This patch adds support for SD module in the device DT. [ gregory.clement@free-electrons.com: - Add more detail in commit log - Sort the dt node in address order - Document the SD slot in the dts ] Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-17arm64: dts: marvell: armada-37xx: Use angle bracket for each register setGregory CLEMENT1-4/+4
When several groups of register address and size are used with reg, then surround each one by angle bracket. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-17arm64: dts: marvell: armada-37xx: Align the compatible stringGregory CLEMENT1-3/+3
This cosmetic patch aligns the compatible string when there are on several lines. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-10Merge tag 'mvebu-dt64-4.12-3' of git://git.infradead.org/linux-mvebu into fixesArnd Bergmann1-3/+70
Pull "mvebu dt64 for 4.12 (part 3)" from Gregory CLEMENT: pinctrl and GPIO description for Armada 37xx SoCs * tag 'mvebu-dt64-4.12-3' of git://git.infradead.org/linux-mvebu: ARM64: dts: marvell: armada37xx: add pinctrl definition ARM64: dts: marvell: Add pinctrl nodes for Armada 3700
2017-05-09Merge tag 'armsoc-dt64' of ↵Linus Torvalds1-1/+17
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Olof Johansson: "Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller changes, but also some new platforms that are worth mentioning: - Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook Plus (Kevin) - Orange Pi PC2 (Allwinner H5) - Freescale LS2088A and LS1088A SoCs - Expanded support for Nvidia Tegra186 (and Jetson TX2)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits) arm64: dts: Add basic DT to support Spreadtrum's SP9860G arm64: dts: exynos: Use - instead of @ for DT OPP entries arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board arm64: dts: juno: add information about L1 and L2 caches arm64: dts: juno: fix few unit address format warnings arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB arm64: marvell: dts: add crypto engine description for 7k/8k arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: dts: marvell: add eMMC support for Armada 37xx arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board arm64: dts: hisi: add SAS nodes for the hip07 SoC arm64: dts: hisi: add RoCE nodes for the hip07 SoC arm64: dts: hisi: add network related nodes for the hip07 SoC arm64: dts: hisi: add mbigen nodes for the hip07 SoC arm64: dts: rockchip: fix the memory size of PX5 Evaluation board arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board ...
2017-04-28ARM64: dts: marvell: armada37xx: add pinctrl definitionGregory CLEMENT1-0/+31
Start to populate the device tree of the Armada 37xx with the pincontrol configuration used on the board providing a dts. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-28ARM64: dts: marvell: Add pinctrl nodes for Armada 3700Gregory CLEMENT1-3/+39
Add the nodes for the two pin controller present in the Armada 37xx SoCs. Initially the node was named gpio1 using the same name that for the register range in the datasheet. However renaming it pinctr_nb (nb for North Bridge) makes more sens. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-11arm64: dts: marvell: add eMMC support for Armada 37xxGregory CLEMENT1-0/+11
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720 DB board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-31 14:36:50 +0300