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2022-11-18arm64: dts: fvp: Add information about L1 and L2 cachesSudeep Holla1-0/+73
Add the information about L1 and L2 caches on FVP RevC platform. Though the cache size is configurable through the model parameters, having default values in the device tree helps to exercise and debug any code utilising the cache information without the need of real hardware. Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-11-18arm64: dts: fvp: Add SPE to Foundation FVPJames Clark1-0/+5
Add SPE DT node to FVP model. If the model doesn't support SPE (e.g., turned off via parameter), the driver will skip the initialisation accordingly and thus is safe. Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20221117102536.237515-1-james.clark@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-11-08arm64: dts: Update cache properties for Arm Ltd platformsPierre Gondois7-0/+10
The DeviceTree Specification v0.3 specifies that the cache node "compatible" and "cache-level" properties are required. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the relevant device trees nodes accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-11-01arm64: dts: juno: Add thermal critical trip pointsCristian Marussi1-0/+14
When thermnal zones are defined, trip points definitions are mandatory. Define a couple of critical trip points for monitoring of existing PMIC and SOC thermal zones. This was lost between txt to yaml conversion and was re-enforced recently via the commit 8c596324232d ("dt-bindings: thermal: Fix missing required property") Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: devicetree@vger.kernel.org Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Fixes: f7b636a8d83c ("arm64: dts: juno: add thermal zones for scpi sensors") Link: https://lore.kernel.org/r/20221028140833.280091-8-cristian.marussi@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-08-15arm64: dts: juno: Add missing MHU secure-irqJassi Brar1-1/+2
The MHU secure interrupt exists physically but is missing in the DT node. Specify the interrupt in DT node to fix a warning on Arm Juno board: mhu@2b1f0000: interrupts: [[0, 36, 4], [0, 35, 4]] is too short Link: https://lore.kernel.org/r/20220801141005.599258-1-jassisinghbrar@gmail.com Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-08-15arm64: dts: arm: juno: Remove legacy Coresight 'slave-mode' propertyRob Herring1-2/+0
The 'slave-mode' property is not valid under 'in-ports' as it was the legacy way to find input ports. Warnings are generated from the Coresight schema: arch/arm64/boot/dts/arm/juno-r1.dtb: funnel@20150000: in-ports:port@0:endpoint: Unevaluated properties are not allowed ('slave-mode' was unexpected) From schema: Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml Link: https://lore.kernel.org/r/20220721212952.1984382-1-robh@kernel.org Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-06-29arm64: dts: juno: Add cache-level property to L2 cachesSudeep Holla3-0/+6
Add the missing cache-level property to L2 caches. This is needed if we need to find the last level cache directly from the device tree cache node. Link: https://lore.kernel.org/r/20220629095959.1115587-1-sudeep.holla@arm.com Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-06-14arm64: dts: arm: adjust whitespace around '='Krzysztof Kozlowski2-30/+30
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Link: https://lore.kernel.org/r/20220526204350.832361-1-krzysztof.kozlowski@linaro.org Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-06-13arm64: dts: arm/juno: Drop erroneous 'mbox-name' propertyRob Herring1-1/+0
The 'mbox-name' property in the Juno mailbox node is undocumented and unused. It's the consumer side of the mailbox binding that have 'mbox-names' properties. Link: https://lore.kernel.org/r/20220610213308.2288094-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-06-13arm64: dts: arm/fvp-base-revc: Remove 'panel-dpi' compatibleRob Herring1-1/+1
The rtsm-display panel timing node was removed in commit 928faf5e3e8d ("arm64: dts: fvp: Remove panel timings"). Without the node, 'panel-dpi' is not needed either. Link: https://lore.kernel.org/r/20220610204057.2203419-1-robh@kernel.org Cc: Robin Murphy <robin.murphy@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-30arm64: dts: juno: Drop useless 'dma-channels/requests' propertiesKrzysztof Kozlowski1-2/+0
The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Another reason is that the number of requests also does not seem right (should be 8). Link: https://lore.kernel.org/r/20220430121902.59895-5-krzysztof.kozlowski@linaro.org Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25arm64: dts: fvp: Align virtio device node names with dtschemaSudeep Holla3-5/+5
Align the virtio mmio device tree node names with the schema to avoid any schema warnings. Link: https://lore.kernel.org/r/20220425135524.1077986-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25arm64: dts: fvp: Add virtio-rng supportDiego Sueiro3-2/+10
The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17, so add the devicetree node to support it. It is disabled by default to avoid any issues with models that doesn't support it. Link: https://lore.kernel.org/r/ac3be672c636091ee1e079cadce776b1fb7e0b2e.1650543392.git.diego.sueiro@arm.com Signed-off-by: Diego Sueiro <diego.sueiro@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-25arm64: dts: Add Arm corstone1000 platform supportRui Miguel Silva4-0/+248
Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. These device trees contains the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and the FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host side of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Link: https://lore.kernel.org/r/20220408131922.3864348-3-rui.silva@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-14arm64: dts: juno: add CTI entries to device treeMike Leach8-5/+302
Add Coresight Cross Trigger Interface(CTI) entries to the device tree for all the Juno variants. Link: https://lore.kernel.org/r/20220413214925.30359-1-mike.leach@linaro.org Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-04-14arm64: dts: juno: Fix SCMI power domain IDs for ETF and CS funnelSudeep Holla2-4/+4
The SCMI power domain ID for all the coresight components is 8 while the previous/older SCPI domain was 0. When adding SCMI variant, couple of instances retained SCPI domain ID by mistake. Fix the same by using the correct SCMI power domain ID of 8. Link: https://lore.kernel.org/r/20220413093547.1699535-1-sudeep.holla@arm.com Fixes: 96bb0954860a ("arm64: dts: juno: Add separate SCMI variants") Cc: Robin Murphy <robin.murphy@arm.com> Reported-by: Mike Leach <Mike.Leach@arm.com> Acked-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-03-08Merge tag 'dt64-cleanup-5.18' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Minor cleanup of ARM64 DTS for v5.18 The DT schema expects DMA controller nodes to follow certain node naming and having dma-cells property. Adjust the DTS files to pass DT schema checks. * tag 'dt64-cleanup-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: lg: align pl330 node name with dtschema arm64: dts: lg: add dma-cells to pl330 node arm64: dts: juno: align pl330 node name with dtschema Link: https://lore.kernel.org/r/20220307173614.157884-1-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-02arm64: dts: juno: align pl330 node name with dtschemaKrzysztof Kozlowski1-1/+1
Fixes dtbs_check warning: dma@7ff00000: $nodename:0: 'dma@7ff00000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220129175621.299254-1-krzysztof.kozlowski@canonical.com
2022-02-21arm64: dts: juno: Add separate SCMI variantsRobin Murphy5-1/+255
While Juno's SCP firmware initially spoke the SCPI protocol, binary releases since 2018, and the newer open-source codebase, only speak SCMI and thus aren't particularly compatibile with the DTs we currently have upstream. Add a parallel set of variant DTs for boards with up-to-date firmware, replacing the SCPI parts with their new SCMI equivalents. Link: https://lore.kernel.org/r/f3516815104f951a05fc0f799681f77d7968f6ac.1645125063.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-01-26arm64: dts: juno: Remove GICv2m dma-rangeRobin Murphy1-2/+1
Although it is painstakingly honest to describe all 3 PCI windows in "dma-ranges", it misses the the subtle distinction that the window for the GICv2m range is normally programmed for Device memory attributes rather than Normal Cacheable like the DRAM windows. Since MMU-401 only offers stage 2 translation, this means that when the PCI SMMU is enabled, accesses through that IPA range unexpectedly lose coherency if mapped as cacheable at the SMMU, due to the attribute combining rules. Since an extra 256KB is neither here nor there when we still have 10GB worth of usable address space, rather than attempting to describe and cope with this detail let's just remove the offending range. If the SMMU is not used then it makes no difference anyway. Link: https://lore.kernel.org/r/856c3f7192c6c3ce545ba67462f2ce9c86ed6b0c.1643046936.git.robin.murphy@arm.com Fixes: 4ac4d146cb63 ("arm64: dts: juno: Describe PCI dma-ranges") Reported-by: Anders Roxell <anders.roxell@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-11-04Merge tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-8/+19
Pull ARM SoC DT updates from Arnd Bergmann: "This is a rather large update for the ARM devicetree files, after a few quieter releases, with 775 total commits and 47 branches pulled into this one. There are 5 new SoC types plus some minor variations, and a total of 60 new machines, so I'm limiting the summary to the main noteworthy items: - Apple M1 gain support for PCI and pinctrl, getting a bit closer to a usable system out of the box. - Qualcomm gains support for Snapdragon 690 (aka SM6350) as well as SM7225, 11 new smartphones, and three additional Chromebooks, and improvements all over the place. - Samsung gains support for ExynosAutov9, an automotive version of their smartphone SoC, but otherwise no major changes. - Microchip adds the SAMA5D29 SoC in the SAMA5 family, and a number of improvements for the recently added SAMA7 family. The LAN966 SoC that was added in the platform code does not have dts files yet. Two board files are added for the older at91sam9g20 SoC - Aspeed supports two additional server boards using their AST2600 as BMC, and improves support for qemu models - Rockchip RK3566/RK3688 gets added, along with six new development boards using RK3328/RK3399/RK3566, and one Chromebook tablet. - Two NAS boxes are added using the ARMv4 based Gemini platform - One new board is added to the Intel Arria SoC FPGA family - Marvell adds one network switch based on Armada 381 and the new MOCHAbin 7040 development board - NXP adds support for the S32G2 automotive SoC, two imx6 based ebook readers, and three additional development boards, which is notably less than their usual additions, but they also gain improvements to their many existing boards - STmicroelectronics adds their stm32mp13 SoC family along with a reference board - Renesas adds new versions of their R-Car Gen3 SoCs and many updates for their older generations - Broadcom adds support for a number of Cisco Meraki wireless controllers, along with two new boards and other updates for BCM53xx/BCM47xx networking SoCs and the Raspberry Pi boards - Mediatek improves support for the MT81xx SoCs used in Chromebooks as well as the MT76xx networking SoCs - NVIDIA adds a number of cleanups and additional support for more hardware on the already supported machines - TI K3 adds support for three new boards along with cleanups - Toshiba adds one board for the Visconti family - Xilinx adds five new ZynqMP based machines - Amlogic support is added for the Radxa Zero and two Jethub home automation controllers, along with changes to other machines - Rob Herring continues his work on fixing dtc warnings all over the tree. - Minor updates for TI OMAP, Mstar, Allwinner/sunxi, Hisilicon, Ux500, Unisoc" * tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (720 commits) arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address arm64: dts: apple: t8103: Add root port interrupt routing arm64: dts: apple: t8103: Add PCIe DARTs arm64: apple: Add PCIe node arm64: apple: Add pinctrl nodes ARM: dts: arm: Update ICST clock nodes 'reg' and node names ARM: dts: arm: Update register-bit-led nodes 'reg' and node names arm64: dts: exynos: add chipid node for exynosautov9 SoC ARM: dts: qcom: fix typo in IPQ8064 thermal-sensor node Revert "arm64: dts: qcom: msm8916-asus-z00l: Add sensors" arm64: dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node arm64: dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property arm64: dts: qcom: sm8350: Add CPU topology and idle-states arm64: dts: qcom: Drop unneeded extra device-specific includes arm64: dts: qcom: msm8916: Drop standalone smem node arm64: dts: qcom: Fix node name of rpm-msg-ram device nodes arm64: dts: qcom: msm8916-asus-z00l: Add sensors arm64: dts: qcom: msm8916-asus-z00l: Add SDCard arm64: dts: qcom: msm8916-asus-z00l: Add touchscreen arm64: dts: qcom: sdm845-oneplus: remove devinfo-size from ramoops node ...
2021-10-26ARM: dts: arm: Update register-bit-led nodes 'reg' and node namesRob Herring1-8/+19
Add a 'reg' entry for register-bit-led nodes on the Arm Ltd platforms. The 'reg' entry is the LED control register address. With this, the node name can be updated to use a generic node name, 'led', and a unit-address. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20211024232003.211484-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-09-26arm: dts: vexpress: Fix motherboard bus 'interrupt-map'Rob Herring1-45/+0
Commit 078fb7aa6a83 ("arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodes") broke booting on a couple of 32-bit VExpress boards. The problem is #address-cells size changed, but interrupt-map was not updated. This results in the timer interrupt (and all the other motherboard interrupts) not getting mapped. As the 'interrupt-map' properties are all just duplicates across boards, just move them into vexpress-v2m.dtsi and vexpress-v2m-rs1.dtsi. Strictly speaking, 'interrupt-map' is dependent on the parent interrupt controller, but it's not likely we'll ever have a different parent than GICv2 on these old platforms. If there was one, 'interrupt-map' can still be overridden. Link: https://lore.kernel.org/r/20210924214221.1877686-1-robh@kernel.org Fixes: 078fb7aa6a83 ("arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodes") Cc: Guillaume Tucker <guillaume.tucker@collabora.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: linux-arm-kernel@lists.infradead.org Reported-by: Reported-by: "kernelci.org bot" <bot@kernelci.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-17arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodesRob Herring7-48/+26
The 'motherboard-bus' node in Arm Ltd boards fails schema checks as 'simple-bus' child nodes must have a unit-address. The 'ranges' handling is also wrong (or at least strange) as the mapping of SMC chip selects should be in the 'arm,vexpress,v2m-p1' node rather than a generic 'simple-bus' node. Either there's 1 too many levels of 'simple-bus' nodes or 'ranges' should be moved down a level. The latter change is more simple, so let's do that. As the 'ranges' value doesn't vary for a given motherboard instance, we can move 'ranges' into the motherboard dtsi files. Link: https://lore.kernel.org/r/20210819184239.1192395-6-robh@kernel.org Cc: Andre Przywara <andre.przywara@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-14arm: dts: vexpress: Drop unused properties from motherboard nodeRob Herring3-6/+0
Drop the '#interrupt-cells' property in the motherboard node which has no effect as the node is neither an interrupt-controller or interrupt-map (that's in the parent node). Drop 'model' as it is not used by software nor documented. Drop 'arm,v2m-memory-map' as it is not used by software. The purpose was to describe which memory map, but that's all described by the DT already. Link: https://lore.kernel.org/r/20210819184239.1192395-4-robh@kernel.org Cc: Andre Przywara <andre.przywara@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-14arm64: dts: arm: drop unused interrupt-names in MHUKrzysztof Kozlowski1-2/+0
The arm,mhu bindings and driver do not define interrupt-names, so drop the property to fix warnings: arch/arm64/boot/dts/arm/juno-r2.dt.yaml: mhu@2b1f0000: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20210820081733.83976-3-krzysztof.kozlowski@canonical.com Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-14arm64: dts: arm: align watchdog and mmc node names with dtschemaKrzysztof Kozlowski2-4/+4
Align the watchdog and mmc device node names with the schema to fix warnings like: mmci@50000: $nodename:0: 'mmci@50000' does not match '^mmc(@.*)?$' wdt@f0000: $nodename:0: 'wdt@f0000' does not match '^watchdog(@.*|-[0-9a-f])?$' Link: https://lore.kernel.org/r/20210820081733.83976-1-krzysztof.kozlowski@canonical.com Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-09-13arm64: dts: fvp: Remove panel timingsRobin Murphy1-12/+0
The simple-panel driver already has hard-coded timings for "arm,rtsm-display", and as such screams at us for trying to override a fixed mode from DT. Since the exact values probably don't matter all that much anyway, just remove the DT node to keep boot quiet. Link: https://lore.kernel.org/r/2701c187cf8e0762df38f68cc069ec2c29a3b5a9.1626283322.git.robin.murphy@arm.com Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-06-09arm64: dts: juno: Update SCPI nodes as per the YAML schemaSudeep Holla1-3/+3
The SCPI YAML schema expects standard node names for clocks and power domain controllers. Fix those as per the schema for Juno platforms. Link: https://lore.kernel.org/r/20210608145133.2088631-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-03-15arm64: dts: juno: Enable more SMMUsRobin Murphy3-1/+8
Now that PCI inbound window restrictions are handled generically between the of_pci resource parsing and the IOMMU layer, and described in the Juno DT, we can finally enable the PCIe SMMU without the risk of DMA mappings inadvertently allocating unusable addresses. Similarly, the relevant support for IOMMU mappings for peripheral transfers has been hooked up in the pl330 driver for ages, so we can happily enable the DMA SMMU without that breaking anything either. Link: https://lore.kernel.org/r/a730070d718cb119f77c8ca1782a0d4189bfb3e7.1614965598.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2021-03-15arm64: dts: juno: Describe PCI dma-rangesRobin Murphy1-0/+4
The PLDA root complex on Juno relies on an address-based lookup table to generate AXI attributes for inbound PCI transactions, and as such will not pass any transaction not matching any programmed address range. The standard firmware configuration programs 3 entries covering the GICv2m MSI doorbell and the 2 DRAM regions, so add a "dma-ranges" property to describe those usable inbound windows. Link: https://lore.kernel.org/r/720d0a9a42e33148fcac45cd39a727093a32bf32.1614965598.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-09-07arm64: dts: arm: Fix SP805 clock-namesAndre Przywara2-2/+2
The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for ARM Ltd. platforms to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Link: https://lore.kernel.org/r/20200828130602.42203-3-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18arm64: dts: juno: Fix SCPI shared mem node nameAndre Przywara1-2/+2
The SRAM DT binding requires child nodes to use a certain node name scheme. Change the naming from scp-shmem to scp-sram to comply with that. Link: https://lore.kernel.org/r/20200513103016.130417-19-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18arm64: dts: juno: Fix GPU interrupt orderAndre Przywara1-4/+4
The Mali binding insists on the GPU interrupts to be in ordered as: job, mmu, gpu. Sort the GPU interrupts and interrupt-names properties accordingly. Link: https://lore.kernel.org/r/20200513103016.130417-17-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18arm64: dts: fvp/juno: Fix bus node namesAndre Przywara5-8/+8
Most Arm Ltd. boards are employing a layered bus structure, to map the hardware design (SoC, motherboard, IOFPGA) and structure the DTs. The "simple-bus" nodes only allow a limited set of node names. Switch to use *-bus to be binding compliant. This relies on a pending dt-schema.git fix for now: https://github.com/devicetree-org/dt-schema/pull/38 Link: https://lore.kernel.org/r/20200513103016.130417-16-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18arm64: dts: fvp: Fix SMMU DT nodeAndre Przywara1-4/+4
The SMMU name in the RevC FVP DT file was not fully binding compliant. Adjust the node name to match the binding's list of allowed names, also shuffle the order of the interrupts to comply with the expected order. Link: https://lore.kernel.org/r/20200513103016.130417-15-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18arm64: dts: fvp/juno: Fix serial node namesAndre Przywara3-9/+9
The UARTs for all Arm Ltd. boards were using "uart" as their node name stub. Replace that with the required "serial" string, to comply with the PL011 DT binding. Link: https://lore.kernel.org/r/20200513103016.130417-14-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18arm64: dts: juno: Use proper DT node name for USBAndre Przywara1-2/+2
The EHCI/OCHI DT binding requires to use "usb" as the node name stub. Replace the existing name with "usb" to comply with the binding. Link: https://lore.kernel.org/r/20200513103016.130417-13-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: fvp: Fix ITS node names and #msi-cellsAndre Przywara2-2/+3
The GIC ITS nodes in the fastmodel DTS files were not fully binding compliant. Use one of the allowed node names, also add the required #msi-cells property for the older model. Link: https://lore.kernel.org/r/20200513103016.130417-12-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: fvp: Fix GIC child nodesAndre Przywara3-48/+48
The GIC DT nodes for the fastmodels were not fully compliant with the DT binding, which has certain expectations about child nodes and their size and address cells values. Use smaller #address-cells and #size-cells values, as the binding requests, and adjust the reg properties accordingly. This requires adjusting the interrupt nexus nodes as well, as one field of the interrupt-map property depends on the GIC's address-size. Since the .dts files share interrupt nexus nodes across different interrupt controllers (GICv2 vs. GICv3), we need to use the only commonly allowed #address-size value of <1> for both. Link: https://lore.kernel.org/r/20200513103016.130417-11-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: juno: Fix GIC child nodesAndre Przywara1-25/+25
The GIC DT nodes for the Juno boards were not fully compliant with the DT binding, which has certain expectations about child nodes and their size and address cells values. Use smaller #address-cells and #size-cells values, as the binding requests, and adjust the reg properties accordingly. This requires adjusting the interrupt nexus nodes as well, as one field of the interrupt-map property depends on the GIC's address-size. Link: https://lore.kernel.org/r/20200513103016.130417-10-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: fvp: Fix GIC compatible namesAndre Przywara2-2/+2
The GIC DT binding only allows certain combinations of DT compatible strings. The somewhat awkward "arm,cortex-a15-gic", "arm,cortex-a9-gic" is not among those. Drop that combination of different "cortex" based strings used for the models, and replace it with the more useful combination including "arm,gic-400". Link: https://lore.kernel.org/r/20200513103016.130417-9-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: juno: Fix mem-timerAndre Przywara1-4/+4
The Juno's mem-timer DT node was not fully compliant with the DT binding, which has certain expectation about child nodes and their size and address cells values. Use a cell size of 1, as the binding requests, and spell out the ranges property to be binding compliant. Link: https://lore.kernel.org/r/20200513103016.130417-8-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: juno: Move fixed devices out of bus nodeAndre Przywara1-79/+79
The devicetree compiler complains when DT nodes without a reg property live inside a (simple) bus node: Warning (simple_bus_reg): Node /bus@8000000/v2m_refclk32khz missing or empty reg/ranges property Move the fixed clocks, the fixed regulator, and the gpio keys to the root node, since they do not depend on any busses. Link: https://lore.kernel.org/r/20200513103016.130417-7-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: fvp: Move fixed clocks out of bus nodeAndre Przywara1-21/+21
The devicetree compiler complains when DT nodes without a reg property live inside a (simple) bus node: Warning (simple_bus_reg): Node /bus@8000000/v2m_refclk32khz missing or empty reg/ranges property Move the fixed clocks to the root node, since they do not depend on any busses. Link: https://lore.kernel.org/r/20200513103016.130417-6-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: fvp: Move fixed devices out of bus nodeAndre Przywara1-68/+68
The devicetree compiler complains when DT nodes without a reg property live inside a (simple) bus node: Warning (simple_bus_reg): Node /bus@8000000/motherboard-bus/v2m_refclk32khz missing or empty reg/ranges property Move the fixed clocks, the fixed regulator, and the config bus subtree to the root node, since they do not depend on any busses. Link: https://lore.kernel.org/r/20200513103016.130417-4-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: fvp/juno: Fix node address fieldsAndre Przywara4-9/+9
The Arm Ltd. boards were using an outdated address convention in the DT node names, by separating the high from the low 32-bits of an address by a comma. Remove the comma from the node name suffix to be DT spec compliant. Link: https://lore.kernel.org/r/20200513103016.130417-3-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-03-25Merge tag 'versatile-dts-v5.7-1' of ↵Arnd Bergmann8-8/+8
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/dt Versatile DTS updates for the v5.7 series take one: - Schema validation for the top level of all ARM reference designs: Integrator, Versatile, RealView, Juno. - Clean up some node names in the trees so they pass validation fine. - Drop the old text bindings. - A top level DMA ranges patch from Rob. * tag 'versatile-dts-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM/arm64: dts: Rename SMB bus to just bus dt-bindings: arm: Drop the non-YAML bindings dt-bindings: arm: Add Versatile Express and Juno YAML schema dt-bindings: arm: Add RealView YAML schema dt-bindings: arm: Add Versatile YAML schema dt-bindings: arm: Add Integrator YAML schema ARM: dts: RealView: Fix the name of the SoC node ARM: dts: Versatile: Use syscon as node name for IB2 ARM: dts: integratorap: Remove top level dma-ranges Link: https://lore.kernel.org/r/CACRpkdbbniYVnsE-pAmU2qCerswserNgEFtY48XQ+_K+DUNC9Q@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-04ARM/arm64: dts: Rename SMB bus to just busLinus Walleij8-8/+8
Discussing the YAML validation schema with the DT maintainers it came out that a bus named "smb@80000000" is not really accepted, and the schema was written to name the static memory bus just "bus@80000000". This change is necessary for the schema to kick in and validate these device trees, else the schema gets ignored. Cc: Rob Herring <robh+dt@kernel.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-23arm64: dts: fast models: Fix FVP PCI interrupt-map propertyMarc Zyngier1-4/+4
The interrupt map for the FVP's PCI node is missing the parent-unit-address cells for each of the INTx entries, leading to the kernel code failing to parse the entries correctly. Add the missing zero cells, which are pretty useless as far as the GIC is concerned, but that the spec requires. This allows INTx to be usable on the model, and VFIO to work correctly. Fixes: fa083b99eb28 ("arm64: dts: fast models: Add DTS fo Base RevC FVP") Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-14 17:56:18 +0300