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The DeviceTree Specification v0.3 specifies that the cache node
"compatible" and "cache-level" properties are required.
Cf. s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the properties
for unified cache is present ('cache-size', ...).
Update the relevant device trees nodes accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add the missing cache-level property to L2 caches. This is needed if
we need to find the last level cache directly from the device tree cache
node.
Link: https://lore.kernel.org/r/20220629095959.1115587-1-sudeep.holla@arm.com
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add Coresight Cross Trigger Interface(CTI) entries to the device tree
for all the Juno variants.
Link: https://lore.kernel.org/r/20220413214925.30359-1-mike.leach@linaro.org
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Now that PCI inbound window restrictions are handled generically between
the of_pci resource parsing and the IOMMU layer, and described in the
Juno DT, we can finally enable the PCIe SMMU without the risk of DMA
mappings inadvertently allocating unusable addresses.
Similarly, the relevant support for IOMMU mappings for peripheral
transfers has been hooked up in the pl330 driver for ages, so we can
happily enable the DMA SMMU without that breaking anything either.
Link: https://lore.kernel.org/r/a730070d718cb119f77c8ca1782a0d4189bfb3e7.1614965598.git.robin.murphy@arm.com
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
ARMv8 Juno/fast models updates for v5.1
1. Support for Fixed Virtual Platforms(FVP) Base RevC model to enable
development of software around the new features available
2. Addition of dynamic-power-coefficient information for CPUs on Juno
3. Miscellaneous changes like re-ordering device nodes, using existing
macros for GIC flags in interrupt-maps and using list instead of
tuple(which is wrong but works as number of interrupt cells is 1)
for mmci interrupts
* tag 'juno-updates-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Add cpu dynamic-power-coefficient information
arm64: dts: fast models: Add DTS fo Base RevC FVP
arm64: dts: juno/fast models: sort couple of device nodes
arm64: dts: models: use list instead of tuple for mmci interrupts
arm64: dts: juno/fast models: using GIC macros instead of hardcoded values
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.
This fixes warnings generated by the DT schema.
Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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A CPUfreq driver, like the scpi driver used on Juno boards, which
provide the Energy Model with power cost information via the PM_OPP
of_dev_pm_opp_get_cpu_power() function, do need the
dynamic-power-coefficient (C) in the device tree.
Method used to obtain the C value:
C is computed by measuring energy (E) consumption of a frequency domain
(FD) over a 10s runtime (t) sysbench workload running at each Operating
Performance Point (OPP) affine to 1 or 2 CPUs of that FD while the other
CPUs of the system are hotplugged out.
By definition all CPUs of a FD have the the same micro-architecture. An
OPP is characterized by a certain frequency (f) and voltage (V) value.
The corresponding power values (P) are calculated by dividing the delta
of the E values between the runs with 2 and 1 CPUs by t.
With n data tuples (P, f, V), n equal to number of OPPs for this
frequency domain, we can solve C by:
P = Pstat + Pdyn
P = Pstat + CV²f
Cx = (Px - P1)/(Vx²fx - V1²f1) with x = {2, ..., n}
The C value is the arithmetic mean out of {C2, ..., Cn}.
Since DVFS is broken on Juno r1, no dynamic-power-coefficient
information has been added to its dts file.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Quentin Perret <quentin.perret@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be
set to "psci".
commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states
bindings examples") attempted to fix this earlier but clearly more is
needed.
Fix the cpu-capacity.txt documentation that uses the incorrect value so
we don't get copy-paste errors like these. Clarify the language in
idle-states.txt by removing the reference to the psci bindings that
might be causing this confusion.
Finally, fix devicetrees of various boards to reflect current
documentation.
[1] Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The latest DTC throws warnings for character '_' in the node names.
Warning (node_name_chars_strict): /thermal-zones/big_cluster: Character '_' not recommended in node name
Warning (node_name_chars_strict): /thermal-zones/little_cluster: Character '_' not recommended in node name
Warning (node_name_chars_strict): /smb@8000000/motherboard/gpio_keys: Character '_' not recommended in node name
Warning (node_name_chars_strict): /pmu_a57: Character '_' not recommended in node name
Warning (node_name_chars_strict): /pmu_a53: Character '_' not recommended in node name
The general recommendation is to use character '-' for all the node names.
This patch fixes the warnings following the recommendation.
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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OF graph endpoint connections must be bidirectional. Fix 2 missing
connections to the STM output port:
Warning (graph_endpoint): /stm@20100000/port/endpoint: graph connection to node '/funnel@20130000/ports/port@1/endpoint' is not bidirectional
Warning (graph_endpoint): /stm@20100000/port/endpoint: graph connection to node '/funnel@20130000/ports/port@1/endpoint' is not bidirectional
Fixes: cde6f9ab10c6 ("arm64: dts: juno: add missing CoreSight STM component")
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU
debug areas are mapped at the same address for all revisions,
like the ETM, even though the CPUs have changed from r1 to r2.
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mathieu Poirier <mathieu.porier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[arranged nodes in ascending order with respect to register addresses]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.
Commit 9a802431c527 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.
This patch adds the information about L1 and L2 caches on all variants
of Juno platform.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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This patch adds the missing CoreSight STM component definition to the
device tree of all the juno variants(r0,r1,r2)
STM component is connected to different funnels depending on Juno
platform variant.
Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
[sudeep.holla@arm.com: minor changelog update and reorganising the STM
node back into juno-base.dtsi to avoid duplication]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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The CoreSight support added for Juno is valid for only Juno r0.
The Juno r1 and r2 variants have additional components and alternative
connection routes between trace source and sinks.
This patch builds on top of the existing r0 support and extends it to
Juno r1/r2 variants.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
[sudeep.holla@arm.com: minor changelog update and major reorganisation of
the common coresight components back into juno-base.dtsi to avoid
duplication, also renamed funnel node names]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Currently juno-clock.dtsi and juno-base.dtsi are nested badly inside
the device tree structure. It's generally good practice to ensure that
individual dtsi stand by themselves at the top of the file.
This patch removes the nesting of the above mentioned dtsi files and
makes them independent.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"A couple of interesting new SoC platforms are now supported, these are
the respective DTS sources:
- Samsung Exynos5433 mobile phone platform, including an (almost)
fully supported phone reference board.
- Hisilicon Hip07 server platform and D05 board, the latest iteration
of their product line, now with 64 Cortex-A72 cores across two
sockets.
- Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product
line, used in Android tablets and ultra-cheap development boards
- NXP LS1046A Communication processor, improving on the earlier
LS1043A with faster CPU cores
- Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810)
mobile phone SoCs
- Early support for the Nvidia Tegra Tegra186 SoC
- Amlogic S905D is a minor variant of their existing Android consumer
product line
- Rockchip PX5 automotive platform, a close relative of their popular
rk3368 Android tablet chips
Aside from the respective evaluation platforms for the above chips,
there are only a few consumer devices and boards added this time:
- Huawei Nexus 6P (Angler) mobile phone
- LG Nexus 5x (Bullhead) mobile phone
- Nexbox A1 and A95X Android TV boxes
- Pine64 development board based on Allwinner A64
- Globalscale Marvell ESPRESSOBin community board based on Armada 3700
- Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board
For the existing platforms, we get bug fixes and new peripheral
support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom,
Rockchip, Berlin, and ZTE"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits)
arm64: dts: fix build errors from missing dependencies
ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible
ARM64: dts: meson-gxl: Add support for Nexbox A95X
ARM64: dts: meson-gxm: Add support for the Nexbox A1
ARM: dts: artpec: add pcie support
arm64: dts: berlin4ct-dmp: add missing unit name to /memory node
arm64: dts: berlin4ct-stb: add missing unit name to /memory node
arm64: dts: berlin4ct: add missing unit name to /soc node
arm64: dts: qcom: msm8916: Add ddr support to sdhc1
arm64: dts: exynos: Enable HS400 mode for eMMC for TM2
ARM: dts: Add xo to sdhc clock node on qcom platforms
ARM64: dts: Add support for Meson GXM
dt-bindings: add rockchip RK1108 Evaluation board
arm64: dts: NS2: Add PCI PHYs
arm64: dts: NS2: enable sdio1
arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash
arm64: tegra: Add NVIDIA P2771 board support
arm64: tegra: Enable PSCI on P3310
arm64: tegra: Add NVIDIA P3310 processor module support
arm64: tegra: Add GPIO controllers on Tegra186
...
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The core and the cluster sleep state entry latencies can't be same as
cluster sleep involves more work compared to core level e.g. shared
cache maintenance.
Experiments have shown on an average about 100us more latency for the
cluster sleep state compared to the core level sleep. This patch fixes
the entry latency for the cluster sleep state.
Fixes: 28e10a8f3a03 ("arm64: dts: juno: Add idle-states to device tree")
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Jon Medhurst (Tixy)" <tixy@linaro.org>
Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This patch adds cpu capacity-dmips-mhz information to Juno R2 boards.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jon Medhurst <tixy@linaro.org>
Cc: Olof Johansson <olof@lixom.net>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Juri Lelli <juri.lelli@arm.com>
[sudeep.holla@arm.com: reformated subject and updated changelog]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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The juno dts have entries for the hwmon scpi, let's create thermal zones
for the temperature sensors described in the Juno ARM Development
Platform Implementation Details.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.
Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.
The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).
The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
memory space
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by
Cortex A72 cores.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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