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path: root/arch/arm/mm/proc-v7-3level.S
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2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333Thomas Gleixner1-13/+1
2017-08-29ARM: 8690/1: lpae: build TTB control register value from scratch in v7_ttb_setupHoeun Ryu1-2/+1
2015-06-02ARM: redo TTBR setup code for LPAERussell King1-9/+5
2014-09-25ARM: 8164/1: mm: clear SCTLR.HA instead of setting it for LPAEWill Deacon1-2/+2
2014-09-02ARM: 8132/1: LPAE: drop wrong carry flag correction after adding TTBR1_OFFSETKonstantin Khlebnikov1-1/+0
2014-08-09ARM: 8114/1: LPAE: load upper bits of early TTBR0/TTBR1Konstantin Khlebnikov1-4/+3
2014-07-24ARM: 8109/1: mm: Modify pte_write and pmd_write logic for LPAESteven Capper1-2/+7
2014-07-18ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+Russell King1-2/+3
2014-04-25ARM: 8037/1: mm: support big-endian page tablesJianguo Wu1-5/+13
2013-07-22ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2Will Deacon1-1/+1
2013-07-15arm: delete __cpuinit/__CPUINIT usage from all ARM usersPaul Gortmaker1-4/+0
2013-05-30ARM: LPAE: accomodate >32-bit addresses for page table baseCyril Chemparathy1-0/+8
2013-05-30ARM: LPAE: factor out T1SZ and TTBR1 computationsCyril Chemparathy1-21/+8
2013-05-30ARM: LPAE: use phys_addr_t in switch_mm()Cyril Chemparathy1-4/+12
2013-04-03ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP insteadWill Deacon1-1/+2
2013-03-04ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.idBen Dooks1-1/+1
2013-02-16ARM: 7650/1: mm: replace direct access to mm->context.id with new macroBen Dooks1-1/+1
2012-11-09ARM: mm: introduce present, faulting entries for PAGE_NONEWill Deacon1-0/+3
2012-11-09ARM: mm: introduce L_PTE_VALID for page table entriesWill Deacon1-1/+1
2011-12-08ARM: LPAE: MMU setup for the 3-level page table formatCatalin Marinas1-0/+150
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