summaryrefslogtreecommitdiff
path: root/arch/arm/mm/cache-l2x0.c
AgeCommit message (Expand)AuthorFilesLines
2015-04-15Merge branches 'misc', 'vdso' and 'fixes' into for-nextRussell King1-17/+16
2015-03-18ARM: 8310/1: l2c: Fix prefetch settings dt parsingFabrice Gasnier1-17/+16
2015-03-10ARM: 8309/1: l2c: enforce use of cache-level propertyFlorian Fainelli1-0/+7
2015-02-12Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds1-209/+230
2015-02-06ARM: 8297/1: cache-l2x0: optimize aurora range operationsArnd Bergmann1-46/+22
2015-02-06ARM: 8296/1: cache-l2x0: clean up aurora cache handlingArnd Bergmann1-73/+38
2015-01-20ARM: cache-l2x0.c: Make it clear that cache-l2x0 handles L310 cache controllerPavel Machek1-1/+1
2015-01-20ARM: l2c: fix commentGeert Uytterhoeven1-1/+1
2015-01-16ARM: 8262/1: l2c: Add support for overriding prefetch settingsTomasz Figa1-0/+54
2015-01-16ARM: 8260/1: l2c: Add interface to ask hypervisor to configure L2CTomasz Figa1-0/+6
2015-01-16ARM: 8259/1: l2c: Refactor the driver to use commit-like interfaceTomasz Figa1-96/+116
2015-01-16ARM: 8258/1: l2c: use l2c_write_sec() for restoring latency and filter regsMarek Szyprowski1-16/+16
2014-10-29ARM: 8183/1: l2c: Improve l2c310_of_parse() error messageFabio Estevam1-2/+2
2014-10-29ARM: 8182/1: l2c: Make l2x0_cache_size_of_parse() return 'int'Fabio Estevam1-6/+16
2014-10-03ARM: 8169/1: l2c: parse cache properties from ePAPR definitionsLinus Walleij1-0/+121
2014-08-05Merge branches 'fixes' and 'misc' into for-nextRussell King1-1/+1
2014-07-18ARM: make it easier to check the CPU part number correctlyRussell King1-1/+1
2014-07-07ARM: l2c: fix revision checkingRussell King1-1/+1
2014-06-29ARM: 8076/1: mm: add support for HW coherent systems in PL310 cacheThomas Petazzoni1-0/+31
2014-05-30ARM: l2c: trial at enabling some Cortex-A9 optimisationsRussell King1-3/+70
2014-05-30ARM: l2c: add warnings for stuff modifying aux_ctrl register valuesRussell King1-3/+22
2014-05-30ARM: l2c: print a warning with L2C-310 caches if the cache size is modifiedRussell King1-0/+2
2014-05-30ARM: l2c: remove old .set_debug methodRussell King1-19/+2
2014-05-30ARM: l2c: always enable non-secure access to lockdown registersRussell King1-2/+21
2014-05-30ARM: l2c: always enable low power modesRussell King1-0/+12
2014-05-30ARM: l2c: add automatic enable of early BRESPRussell King1-3/+22
2014-05-30ARM: l2c: move L2 cache register saving to a more sensible locationRussell King1-12/+22
2014-05-30ARM: l2c: check that DT files specify the required "cache-unified" propertyRussell King1-0/+4
2014-05-30ARM: l2c: fix register namingRussell King1-28/+29
2014-05-30ARM: l2c: implement L2C-310 erratum 752271 in core L2C codeRussell King1-1/+17
2014-05-30ARM: l2c: provide generic hook to intercept writes to secure registersRussell King1-12/+30
2014-05-30ARM: l2c: move way size calculation data into l2c_init_dataRussell King1-9/+20
2014-05-30ARM: l2c: add decode for L2C-220 cache waysRussell King1-0/+1
2014-05-30ARM: l2c: move type string into l2c_init_data structureRussell King1-7/+13
2014-05-30ARM: l2c: remove obsolete l2x0 ops for non-OF initRussell King1-206/+0
2014-05-30ARM: l2c: convert Broadcom L2C-310 to new codeRussell King1-16/+11
2014-05-30ARM: l2c: add L2C-220 specific handlersRussell King1-10/+157
2014-05-30ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementationsRussell King1-22/+36
2014-05-30ARM: l2c: implement L2C-310 erratum 588369 as a method overrideRussell King1-0/+69
2014-05-30ARM: l2c: implement L2C-310 erratum 727915 as a method overrideRussell King1-0/+20
2014-05-30ARM: l2c: add L2C-210 specific handlersRussell King1-1/+122
2014-05-30ARM: l2c: move pl310_set_debug() into l2c-310 codeRussell King1-8/+6
2014-05-30ARM: l2c: simplify l2x0 unlocking codeRussell King1-17/+8
2014-05-30ARM: l2c: clean up save/resume functionsRussell King1-57/+52
2014-05-30ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OFRussell King1-74/+77
2014-05-30ARM: l2c: clean up L2 cache initialisation messagesRussell King1-3/+4
2014-05-30ARM: l2c: implement fixups for L2 cache controller quirks/errataRussell King1-11/+101
2014-05-30ARM: l2c: move aurora broadcast setup to enable functionRussell King1-13/+15
2014-05-30ARM: l2c: only write the auxiliary control register if requiredRussell King1-1/+3
2014-05-30ARM: l2c: write auxctrl register before unlockingRussell King1-5/+5
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-08 00:44:18 +0300