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path: root/arch/arm/mach-tegra/reset-handler.S
AgeCommit message (Expand)AuthorFilesLines
2015-05-04ARM: tegra20: Store CPU "resettable" status in IRAMDmitry Osipenko1-3/+7
2014-11-17ARM: tegra: Re-add removed SoC id macro to tegra_resume()Dmitry Osipenko1-0/+1
2014-07-17ARM: tegra: Use a function to get the chip IDThierry Reding1-1/+2
2014-07-17ARM: tegra: Sort includes alphabeticallyThierry Reding1-2/+2
2014-05-30ARM: l2c: tegra: convert to common l2c310 early resume functionalityRussell King1-8/+3
2013-10-19ARM: tegra: make tegra_resume can work with current and later chipsJoseph Lo1-8/+5
2013-08-12ARM: tegra: add common resume handling code for LP1 resumingJoseph Lo1-0/+13
2013-07-19ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15Joseph Lo1-0/+1
2013-07-19ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9Joseph Lo1-2/+5
2013-06-05ARM: tegra: remove ifdef in the tegra_resumeJoseph Lo1-3/+1
2013-05-23ARM: tegra114: add CPU hotplug supportJoseph Lo1-3/+12
2013-05-23ARM: tegra: make tegra_resume can work for Tegra114Joseph Lo1-4/+9
2013-05-23ARM: tegra: add an assembly marco to check Tegra SoC IDJoseph Lo1-16/+9
2013-04-18ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabledJoseph Lo1-0/+1
2013-03-12ARM: tegra: don't unlock MMIO access to DBGLARJoseph Lo1-3/+0
2013-03-12ARM: tegra: add CPU errata WARs to Tegra reset handlerStephen Warren1-6/+39
2013-01-28ARM: tegra: make device can run on UPJoseph Lo1-0/+239
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