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path: root/arch/arm/mach-tegra/irq.c
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2015-03-15ARM: tegra: remove old LIC supportMarc Zyngier1-199/+2
Now that all DTs have been updated, entierely drop support for the non-DT code. This is likely to break platforms that do not update their DT, so print a warning at boot time. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-7-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-15ARM: tegra: skip gic_arch_extn setup if DT has a LIC nodeMarc Zyngier1-0/+12
If we detect that our DT has a LIC node, don't setup gic_arch_extn, and skip tegra_legacy_irq_syscore_init as well. This is only a temporary measure until that code is removed for good. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-4-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-15ARM: tegra: irq: nuke leftovers from non-DT supportMarc Zyngier1-8/+0
The GIC is now always initialized from DT on tegra, and there is no point in keeping non-DT init code. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-27ARM: tegra: irq: fix buggy usage of irq_data irq fieldMarc Zyngier1-11/+11
The crazy gic_arch_extn thing that Tegra uses contains multiple references to the irq field in struct irq_data, and uses this to directly poke hardware register. But irq is the *virtual* irq number, something that has nothing to do with the actual HW irq (stored in the hwirq field). And once we put the stacked domain code in action, the whole thing explodes, as these two values are *very* different: root@bacon-fat:~# cat /proc/interrupts CPU0 CPU1 16: 25801 2075 GIC 29 twd 17: 0 0 GIC 73 timer0 112: 0 0 GPIO 58 c8000600.sdhci cd 123: 0 0 GPIO 69 c8000200.sdhci cd 279: 1126 0 GIC 122 serial 281: 0 0 GIC 70 7000c000.i2c 282: 0 0 GIC 116 7000c400.i2c 283: 0 0 GIC 124 7000c500.i2c 284: 300 0 GIC 85 7000d000.i2c [...] Just replacing all instances of irq with hwirq fixes the issue. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-17ARM: tegra: Sort includes alphabeticallyThierry Reding1-4/+4
If these aren't sorted alphabetically, then the logical choice is to append new ones, however that creates a lot of potential for conflicts because every change will then add new includes in the same location. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-07-19ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM entryJoseph Lo1-0/+40
There is a difference between GICv1 and v2 when CPU in power management mode (aka CPU power down on Tegra). For GICv1, IRQ/FIQ interrupt lines going to CPU are same lines which are also used for wake-interrupt. Therefore, we cannot disable the GIC CPU interface if we need to use same interrupts for CPU wake purpose. This creates a race condition for CPU power off entry. Also, in GICv1, disabling GICv1 CPU interface puts GICv1 into bypass mode such that incoming legacy IRQ/FIQ are sent to CPU, which means disabling GIC CPU interface doesn't really disable IRQ/FIQ to CPU. GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. When the IRQ/FIQ not being driver by the CPU interface, each interrupt output signal can be deasserted rather than being driven by the legacy interrupt input. So the wake-event can be used as wakeup signals to SoC (system power controller). To prevent race conditions and ensure proper interrupt routing on Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier call-back to reprogram the GIC CPU interface on PM entry. The GIC CPU interface will be reset back to its normal state by the common GIC CPU PM exit callback when the CPU wakes up. Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04ARM: tegra: irq: add wake up handlingJoseph Lo1-1/+95
Add the wake up handling for legacy irq controller, and using IRQCHIP_MASK_ON_SUSPEND for wake irq handling. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-06Merge tag 'tegra-for-3.9-soc-cpuidle' of ↵Olof Johansson1-0/+15
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: cpuidle enhancements This pull request implements a new "LP2" cpuidle state for Tegra20, which makes use of the couple cpuidle feature. It is based on (most of) the previous pull request, with tag tegra-for-3.9-soc-usb. * tag 'tegra-for-3.9-soc-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops ARM: tegra20: cpuidle: add powered-down state for secondary CPU ARM: tegra: add pending SGI checking API Signed-off-by: Olof Johansson <olof@lixom.net>
2013-01-28ARM: tegra: add pending SGI checking APIJoseph Lo1-0/+15
The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes. For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-12irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.hRob Herring1-2/+1
Now that we have GIC moved to drivers/irqchip and all GIC DT init for platforms using irqchip_init, move gic.h and update the remaining includes. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Anton Vorontsov <avorontsov@mvista.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Samuel Ortiz <sameo@linux.intel.com>
2012-11-05ARM: tegra: move iomap.h to mach-tegraStephen Warren1-2/+1
Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../iomap.h" becaue of this change. uncompress.h will soon be deleted in later multi-platform/single-zImage patches. debug-macro.S will need to continue to include this header using an explicit relative path, to avoid duplicating the physical->virtual address mapping that iomap.h dictates. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-02-06ARM: tegra: add support for tegra30 interruptsPeter De Schrijver1-4/+16
Tegra30 has 1 extra legacy interrupt controller. Use the GIC ITLinesNumber field to determine how many interrupt controllers we have and initialize appropriately. Also make room for the extra tegra30 interrupts by moving the GPIO IRQ base. This shouldn't affect existing code as it determines the correct IRQ number for GPIOs using TEGRA_GPIO_TO_IRQ(). Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2011-12-28Merge branch 'tegra/dt' into next/dtArnd Bergmann1-2/+8
* tegra/dt: arm/tegra: Seaboard: Add GPIO key device tree nodes arm/dt: Add ADT7461 to Seaboard arm/dt: tegra: Use new compatible value for DVC I2C controller arm/tegra: initial device tree for tegra30 arm/tegra: convert tegra20 to GIC devicetree binding arm/dt: tegra: Fix SDHCI nodes to match board files arm/dt: tegra: Fix serial nodes to match board files arm/dt: tegra: Fix I2C nodes to match board files arm/dt: tegra: Remove /chosen node arm/dt: tegra: Remove /memreserve/ from device-tree files arm/tegra: board-dt: Enable audio-related clocks arm/tegra: board-dt: Fix AUXDATA typo arm/dt: tegra: add dts file for paz00 arm/tegra: Add device-tree support for TrimSlice board arm/dt: tegra: Clean up I2S and DAS nodes USB: ehci-tegra: add probing through device tree arm/dt: add basic usb nodes to tegra device trees arm/tegra: fix variable formatting in makefile Conflicts: arch/arm/mach-tegra/Makefile
2011-12-08arm/tegra: convert tegra20 to GIC devicetree bindingpdeschrijver@nvidia.com1-2/+8
Convert tegra20 IRQ intialization to the GIC devicetree binding. Modify the interrupt definitions in the dts files according to Documentation/devicetree/bindings/arm/gic.txt v3 (swarren): * Moved of_irq_init() call into board-dt.c to avoid ifdef'ing it. - Even with a dummy replacement if !CONFIG_OF, the reference from tegra_dt_irq_match[] to gic_of_init() would still have to be ifdef'd - It's plausible that tegra_dt_irq_match[] may need to contain more entries in the future, and defining what they are seems more suitable for board-dt.c than irq.c v2 (swarren): * Removed some stale GIC init code from board-dt.c * Undid some accidental 0x -> 0x0 search/replace. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> [olof: added include of <asm/hardware/gic.h> for compile to pass] Signed-off-by: Olof Johansson <olof@lixom.net>
2011-12-08arm/tegra: remove unused definespdeschrijver@nvidia.com1-4/+0
PPI_NR is never used in arch/arm/mach-tegra/irq.c. Remove it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2011-05-11ARM: tegra: irq: Add tegra_eoiColin Cross1-0/+9
Implement irq_eoi to allow the GIC irq chip flow controller to be changed to fasteoi. Signed-off-by: Colin Cross <ccross@android.com>
2011-05-11ARM: tegra: irq: Move legacy_irq.c into irq.cColin Cross1-12/+65
Now that irq.c is just an interface layer between the gic and legacy_irq.c, move the contents of legacy_irq.c into irq.c. Signed-off-by: Colin Cross <ccross@android.com>
2011-05-11ARM: tegra: irq: Remove PM supportColin Cross1-66/+0
Tegra PM irq support is being improved, remove it for now until the rest of the platform gets PM support. Signed-off-by: Colin Cross <ccross@android.com>
2011-05-11ARM: tegra: irq: convert to gic arch extensionsColin Cross1-38/+16
Replace the ugly hack that inserts legacy irq controller calls into the irq call paths by reading and replacing the gic irq chip with the new gic arch extensions. Signed-off-by: Colin Cross <ccross@android.com>
2011-03-29arm: Fold irq_set_chip/irq_set_handlerThomas Gleixner1-2/+1
Use irq_set_chip_and_handler() instead. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-29arm: Cleanup the irq namespaceThomas Gleixner1-3/+3
Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-10ARM: tegra: irq: Implement retriggerColin Cross1-1/+16
Signed-off-by: Colin Cross <ccross@android.com>
2011-02-10ARM: tegra: irq: Add support for suspend wake sourcesColin Cross1-101/+75
Signed-off-by: Colin Cross <ccross@android.com>
2011-02-10ARM: tegra: Add prototypes for subsystem suspend functionsColin Cross1-0/+1
Signed-off-by: Colin Cross <ccross@android.com>
2011-01-27ARM: tegra: irq: Rename gic pointers to avoid conflictsColin Cross1-9/+9
A future patch will export gic_mask_irq and gic_unmask_irq. Rename the pointers in arch/arm/mach-tegra/irq.c to avoid a compile error. Signed-off-by: Colin Cross <ccross@android.com>
2011-01-13ARM: tegra: irq_data conversion.Lennert Buytenhek1-18/+18
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
2010-12-14ARM: GIC: provide a single initialization function for boot CPURussell King1-2/+2
Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-22[ARM] tegra: add suspend and mirror irqs to legacy controllerGary King1-0/+137
mirror IRQ enable and disable operations on the legacy PPI system interrupt controller, since the legacy controller is responsible for responding to wakeup interrupts when the CPU is in LP2 idle mode save the irq controller state on suspend and restore on resume Signed-off-by: Gary King <gking@nvidia.com>
2010-08-06[ARM] tegra: Add IRQ supportErik Gilling1-0/+34
v2: fixes from Russell King - include linux/io.h instead of asm/io.h and mach/io.h Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
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