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2023-09-27ARM: shmobile: sh73a0: Reserve boot area when SMP is enabledGeert Uytterhoeven1-2/+8
CPU core bringup on SH-Mobile AG5 uses the SYS Boot Address (SBAR) and Address Translation Area (APARMBAREA) registers to specify the base address and size of the boot area of the System CPU. With this enabled, when the System CPU accesses a physical address in the range from zero up to the configured size, the top address bits are replaced by those specified in the SBAR register. Hence any device residing in this low part of physical address space cannot be accessed. Prevent conflicts by reserving this memory region using request_mem_region(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20eb4e7fca9c41a34500fc5984602b41006b4575.1693409184.git.geert+renesas@glider.be
2023-09-27ARM: shmobile: r8a7779: Reserve boot area when SMP is enabledGeert Uytterhoeven1-1/+8
CPU core bringup on R-Car H1 uses the ARM Reset Vector Address Register (AVECR) to specify the base address and size of the boot area of the System CPU. With this enabled, when the System CPU accesses a physical address in the range from zero up to the configured size, the top address bits are replaced by those specified in the AVECR register. Hence any device residing in this low part of physical address space cannot be accessed, Prevent conflicts by reserving this memory region using request_mem_region(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/924961188abdf2adb52167edb7ed848a6efcca39.1693409184.git.geert+renesas@glider.be
2023-09-27ARM: shmobile: rcar-gen2: Reserve boot area when SMP is enabledGeert Uytterhoeven1-0/+5
CPU core bringup on R-Car Gen2 SoCs uses the Cortex-A7/A15 Boot Address Register to specify the boot area of the System CPU. With this enabled, when the System CPU accesses a physical address in the range from 0x0 to 0x3ffff, the top address bits are replaced by those specified in the SBAR register. Hence any device residing in the low 256 KiB of physical address space cannot be accessed. Prevent conflicts by reserving this memory region using request_mem_region(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/091150233acb0557a2ad3294d67b2adb6758670c.1693409184.git.geert+renesas@glider.be
2023-09-25ARM: shmobile: rcar-gen2: Remove unneeded once handlingGeert Uytterhoeven1-4/+0
rcar_gen2_pm_init() is only called from the smp_operations.smp_prepare_cpus() callback, which is called at most once. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/116ef21e5f495432d913315bdc25fbc30edcf2e1.1693409184.git.geert+renesas@glider.be
2023-07-25ARM: shmobile: rcar-gen2: Drop unused OF includesRob Herring1-1/+0
of_platform.h is not needed, so drop it. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230717225614.3214179-1-robh@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-29ARM: mm: Make virt_to_pfn() a static inlineLinus Walleij2-2/+2
Making virt_to_pfn() a static inline taking a strongly typed (const void *) makes the contract of a passing a pointer of that type to the function explicit and exposes any misuse of the macro virt_to_pfn() acting polymorphic and accepting many types such as (void *), (unitptr_t) or (unsigned long) as arguments without warnings. Doing this is a bit intrusive: virt_to_pfn() requires PHYS_PFN_OFFSET and PAGE_SHIFT to be defined, and this is defined in <asm/page.h>, so this must be included *before* <asm/memory.h>. The use of macros were obscuring the unclear inclusion order here, as the macros would eventually be resolved, but a static inline like this cannot be compiled with unresolved macros. The naive solution to include <asm/page.h> at the top of <asm/memory.h> does not work, because <asm/memory.h> sometimes includes <asm/page.h> at the end of itself, which would create a confusing inclusion loop. So instead, take the approach to always unconditionally include <asm/page.h> at the end of <asm/memory.h> arch/arm uses <asm/memory.h> explicitly in a lot of places, however it turns out that if we just unconditionally include <asm/memory.h> into <asm/page.h> and switch all inclusions of <asm/memory.h> to <asm/page.h> instead, we enforce the right order and <asm/memory.h> will always have access to the definitions. Put an inclusion guard in place making it impossible to include <asm/memory.h> explicitly. Link: https://lore.kernel.org/linux-mm/20220701160004.2ffff4e5ab59a55499f4c736@linux-foundation.org/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-30ARM: sh-mobile: Use of_cpu_node_to_id() to read CPU node 'reg'Rob Herring1-20/+16
Replace open coded CPU nodes reading of "reg" and translation to logical ID with of_cpu_node_to_id(). The original code called of_parse_phandle() CONFIG_NR_CPUS times regardless of the length of 'cpus'. Optimize the loop to bail out once of_parse_phandle() fails as the end of 'cpus' property has been reached. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230327205228.573456-1-robh@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-28ARM: shmobile: Drop selecting GPIOLIB and PINCTRLLad Prabhakar1-2/+0
Do not automatically select the GPIOLIB and PINCTRL config options as they are already automatically selected as part of the SOC_RENESAS config option in drivers/soc/renesas/Kconfig. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20221027112300.77184-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-18ARM: shmobile: Drop selecting SOC_BUSLad Prabhakar1-1/+0
Don't automatically select the SOC_BUS config option as we already have automatically selected it as part of the SOC_RENESAS config option [0] as renesas-soc.c [1] uses the APIs provided by SOC_BUS config option. [0] drivers/soc/renesas/Kconfig [1] drivers/soc/renesas/renesas-soc.c Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220915233852.415407-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05ARM: shmobile: rcar-gen2: Increase refcount for new referenceLiang He1-1/+4
In rcar_gen2_regulator_quirk(), for_each_matching_node_and_match() will automatically increase and decrease the refcount. However, we should call of_node_get() for the new reference created in 'quirk->np'. Besides, we also should call of_node_put() before the 'quirk' being freed. Signed-off-by: Liang He <windhl@126.com> Link: https://lore.kernel.org/r/20220701121804.234223-1-windhl@126.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05ARM: shmobile: rcar-gen2: Drop comma after OF match table sentinelGeert Uytterhoeven1-1/+1
It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Add a comment to clarify the purpose of the empty element. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/baaa4df6284401eb126573eb1c8ea5a88705cc37.1646311858.git.geert+renesas@glider.be
2022-05-05ARM: shmobile: Drop commas after dt_compat sentinelsGeert Uytterhoeven9-10/+10
It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ab4acc22eebb96a0747eb301c878b24b1200736a.1646311825.git.geert+renesas@glider.be
2022-03-17ARM: remove support for NOMMU ARMv4/v5Arnd Bergmann1-1/+1
It is possible to build MMU-less kernels for Cortex-M base microcrontrollers as well as a couple of older platforms that have not been converted to CONFIG_ARCH_MULTIPLATFORM, specifically ep93xx, footbridge, dove, sa1100 and s3c24xx. It seems unlikely that anybody has tested those configurations in recent years, as even building them is frequently broken. A patch I submitted caused another build time regression in this configuration. I sent a patch for that, but it seems better to also remove the option entirely, leaving ARMv7-M as the only supported Arm NOMMU target for simplicity. A couple of platforms have dependencies on CONFIG_MMU, those can all be removed now. Notably, mach-integrator tries to support MMU-less CPU cores, but those have not actually been selectable for a long time. This addresses several build failures in randconfig builds that have accumulated over the years. Cc: Vladimir Murzin <vladimir.murzin@arm.com> Cc: Russell King <linux@armlinux.org.uk> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-11-15ARM: shmobile: rcar-gen2: Add missing of_node_put()Wan Jiabing1-1/+4
Fix following coccicheck warning: ./arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c:156:1-33: Function for_each_matching_node_and_match should have of_node_put() before break and goto. Early exits from for_each_matching_node_and_match() should decrement the node reference counter. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Link: https://lore.kernel.org/r/20211018014503.7598-1-wanjiabing@vivo.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-23ARM: shmobile: Stop using __raw_*() I/O accessorsGeert Uytterhoeven5-18/+18
There is no reason to keep on using the __raw_{read,write}l() I/O accessors in Renesas ARM platform code. Switch to using the plain {read,write}l() I/O accessors, to have a chance that this works on big-endian. Suggested-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20201117142447.2205664-1-geert+renesas@glider.be
2020-11-23ARM: shmobile: sh73a0: Remove obsolete static mappingGeert Uytterhoeven1-19/+0
There are no more users of the statically mapped IOMEM region on SH-Mobile AG5. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117103022.2136527-8-geert+renesas@glider.be
2020-11-23ARM: shmobile: sh73a0: Use ioremap() to map SMP registersGeert Uytterhoeven1-11/+22
Replace using the legacy IOMEM() macro to map various registers related to secondary CPU bringup by ioremap(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117103022.2136527-7-geert+renesas@glider.be
2020-11-23ARM: shmobile: sh73a0: Use ioremap() to map L2C registersGeert Uytterhoeven1-1/+1
Replace using the legacy IOMEM() macro to map the L2C registers by ioremap(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117103022.2136527-6-geert+renesas@glider.be
2020-11-23ARM: shmobile: r8a7779: Remove obsolete static mappingsGeert Uytterhoeven1-24/+0
There are no more users of the statically mapped IOMEM regions on R-Car H1. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117103022.2136527-5-geert+renesas@glider.be
2020-11-23ARM: shmobile: r8a7779: Use ioremap() to map SMP registersGeert Uytterhoeven1-3/+9
Replace using the legacy IOMEM() macro to map the ARM Reset Vector Address Register (AVECR) by ioremap(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117103022.2136527-4-geert+renesas@glider.be
2020-11-23ARM: shmobile: r8a7779: Use ioremap() to map INTC2 registersGeert Uytterhoeven1-14/+20
Replace using the legacy IOMEM() macro to map various registers related to INTC2 configuration by ioremap(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117103022.2136527-3-geert+renesas@glider.be
2020-11-23ARM: shmobile: r8a7778: Introduce HPBREG_BASEGeert Uytterhoeven1-1/+3
Replace the hardcoded address of the HPB Register block by a macro. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117103022.2136527-2-geert+renesas@glider.be
2020-10-24Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2-4/+2
Pull ARM SoC platform updates from Olof Johansson: "SoC changes, a substantial part of this is cleanup of some of the older platforms that used to have a bunch of board files. In particular: - Remove non-DT i.MX platforms that haven't seen activity in years, it's time to remove them. - A bunch of cleanup and removal of platform data for TI/OMAP platforms, moving over to genpd for power/reset control (yay!) - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them closer to multiplatform support (not quite there yet, but getting close). There are a few other changes too, smaller fixlets, etc. For new platform support, the primary ones are: - New SoC: Hisilicon SD5203, ARM926EJ-S platform. - Cpufreq support for i.MX7ULP" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits) ARM: mstar: Select MStar intc ARM: stm32: Replace HTTP links with HTTPS ones ARM: debug: add UART early console support for SD5203 ARM: hisi: add support for SD5203 SoC ARM: omap3: enable off mode automatically clk: imx: imx35: Remove mx35_clocks_init() clk: imx: imx31: Remove mx31_clocks_init() clk: imx: imx27: Remove mx27_clocks_init() ARM: imx: Remove unused definitions ARM: imx35: Retrieve the IIM base address from devicetree ARM: imx3: Retrieve the AVIC base address from devicetree ARM: imx3: Retrieve the CCM base address from devicetree ARM: imx31: Retrieve the IIM base address from devicetree ARM: imx27: Retrieve the CCM base address from devicetree ARM: imx27: Retrieve the SYSCTRL base address from devicetree ARM: s3c64xx: bring back notes from removed debug-macro.S ARM: s3c24xx: fix Wunused-variable warning on !MMU ARM: samsung: fix PM debug build with DEBUG_LL but !MMU MAINTAINERS: mark linux-samsung-soc list non-moderated ARM: imx: Remove remnant board file support pieces ...
2020-10-06dma-mapping: merge <linux/dma-contiguous.h> into <linux/dma-map-ops.h>Christoph Hellwig1-1/+1
Merge dma-contiguous.h into dma-map-ops.h, after removing the comment describing the contiguous allocator into kernel/dma/contigous.c. Signed-off-by: Christoph Hellwig <hch@lst.de>
2020-09-10ARM: shmobile: rcar-gen2: Make rcar_gen2_{timer_init, reserve}() staticGeert Uytterhoeven2-4/+2
As of commit 1e90fea35b80cfe1 ("ARM: shmobile: r8a7791: Use common R-Car Gen2 machine definition"), there are no more users of rcar_gen2_timer_init() and rcar_gen2_reserve() outside arch/arm/mach-shmobile/setup-rcar-gen2.c. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200908074403.4379-1-geert+renesas@glider.be
2020-04-28ARM: shmobile: r8a7742: Basic SoC supportLad Prabhakar1-0/+2
Add minimal support for the RZ/G1H (R8A7742) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1587678050-23468-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-02-17ARM: shmobile: Replace <linux/clk-provider.h> by <linux/of_clk.h>Geert Uytterhoeven1-1/+1
The R-Car Gen2 platform code is not a clock provider, and just needs to call of_clk_init(). Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200212100830.446-6-geert+renesas@glider.be
2020-02-10ARM: shmobile: Enable ARM_GLOBAL_TIMER on Cortex-A9 MPCore SoCsGeert Uytterhoeven2-2/+0
SH-Mobile AG5 and R-Car H1 SoCs are based on the Cortex-A9 MPCore, which includes a global timer. Enable the ARM global timer on these SoCs, which will be used for: - the scheduler clock, improving scheduler accuracy from 10 ms to 3 or 4 ns, - delay loops, allowing removal of calls to shmobile_init_delay() from the corresponding machine vectors. Note that when using an old DTB lacking the global timer, the kernel will still work. However, loops-per-jiffies will no longer be preset, and the delay loop will need to be calibrated during boot. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191211135222.26770-5-geert+renesas@glider.be
2020-01-06remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig4-7/+7
ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
2019-10-25ARM: shmobile: rcar-gen2: Drop legacy DT clock supportGeert Uytterhoeven1-1/+0
As of commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files use the unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. Hence remove backward compatibility with old R-Car Gen2 device trees describing a hierarchical representation of the various CPG and MSTP clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191016150939.30620-1-geert+renesas@glider.be
2019-05-31ARM: mach-shmobile: Don't init CNTVOFF/counter if PSCI is availableOleksandr Tyshchenko1-0/+17
If PSCI is available then most likely we are running on PSCI-enabled U-Boot which, we assume, has already taken care of resetting CNTVOFF and updating counter module before switching to non-secure mode and we don't need to. As the psci_smp_available() helper always returns false if CONFIG_SMP is disabled, it can't be used safely as an indicator of PSCI usage. For that reason, we check for the mandatory PSCI operation to be available. Please note, an extra check to prevent secure_cntvoff_init() from being called for secondary CPUs in headsmp-apmu.S is not needed, as SMP code for APMU based system is not executed if PSCI is in use. Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18ARM: shmobile: fix a leaked reference by adding missing of_node_putWen Yang1-0/+1
The call to of_get_next_child returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./arch/arm/mach-shmobile/pm-rcar-gen2.c:77:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 66, but without a corresponding object release within this function. ./arch/arm/mach-shmobile/pm-rcar-gen2.c:85:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 66, but without a corresponding object release within this function. ./arch/arm/mach-shmobile/pm-rcar-gen2.c:90:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 66, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18ARM: shmobile: porter: enable R-Car Gen2 regulator quirkMarek Vasut1-2/+4
Porter needs the regulator quirk, just like the other boards. But unlike the other boards, the Porter uses DA9063L, which is at 0x5a. Otherwise, DA9063L and DA9210 IRQ line is still connected to CPU IRQ2 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-07ARM: shmobile: Fix R-Car Gen2 regulator quirkMarek Vasut1-0/+5
The quirk code currently detects all compatible I2C chips with a shared IRQ line on all I2C busses, adds them into a list, and registers a bus notifier. For every chip for which the bus notifier triggers, the quirk code performs I2C transfer on that I2C bus for all addresses in the list. The problem is that this may generate transfers to non-existing chips on systems with multiple I2C busses. This patch adds a check to verify that the I2C bus to which the chip with shared IRQ is attached to matches the I2C bus of the chip which triggered the bus notifier and only starts the I2C transfer if they match. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Tested-by: Nguyen Viet Dung <dung.nguyen.aj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30ARM: shmobile: R-Mobile: Move pm-rmobile to drivers/soc/renesas/Geert Uytterhoeven3-358/+0
The pm-rmobile driver is really a driver for the System Controller (SYSC) found in R-Mobile SoCs. An equivalent driver for R-Car SoCs is already located under drivers/soc/renesas/. Hence move the pm-rmobile driver from arch/arm/mach-shmobile/ to drivers/soc/renesas/, and rename it to rmobile-sysc. Enable compile-testing on non-ARM and non-R-Mobile SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-30ARM: shmobile: R-Mobile: Clean up struct rmobile_pm_domainGeert Uytterhoeven2-41/+18
Commit 59b89af1d5551c12 ("ARM: shmobile: sh7372: Remove Legacy C SoC code") removed the last user of the rmobile_pm_domain.resume() callback. Commit 44d88c754e57a6d9 ("ARM: shmobile: Remove legacy SoC code for R-Mobile A1") removed the last user of the rmobile_pm_domain.no_debug flag and of the "pm-rmobile.h" header file (outside the actual driver). Hence remove no longer used rmobile_pm_domain members, and absorb the header file into the driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-16ARM: shmobile: Move SoC Kconfig symbols to drivers/soc/renesas/Geert Uytterhoeven1-126/+0
For consistency with arm64, where vendors have a single Kconfig symbol in arch/arm64/Kconfig.platforms. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-16ARM: shmobile: Hide ARCH_RZN1 to improve consistencyGeert Uytterhoeven1-5/+4
Unlike all other family-specific Kconfig symbols for Renesas ARM SoCs, ARCH_RZN1 is user-visible. As this symbol is already selected by the SoC-specific ARCH_R9A06G032 symbol, there is no need for that. Hide ARCH_RZN1 from the user, and move it up, where all other family-specific Kconfig symbols live. Drop the select of CPU_V7, as this is already implied by the dependency of ARCH_RENESAS on ARCH_MULTI_V7. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-16ARM: shmobile: sh73a0: Remove obsolete inclusion of <asm/smp_twd.h>Geert Uytterhoeven1-1/+0
As of commit 9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code for SH-Mobile AG5"), this header file is no longer used. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-16ARM: shmobile: Restrict TWD support to SoCs that have itGeert Uytterhoeven1-1/+2
Currently support for the ARM Timer and Watchdog Unit is included unconditionally, while only some Renesas multicore Cortex-A9 SoCs have a TWD. This decreases kernel image size by ca. 2 KiB on SoCs without a TWD. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-16ARM: shmobile: Restrict SCU support to SoCs that have itGeert Uytterhoeven1-1/+3
Currently support for the ARM Cortex-A9 Snoop Control Unit is included unconditionally, while only Renesas multicore Cortex-A9 SoCs have this kind of SCU. This decreases kernel image size by ca. 300 bytes on SoCs without such an SCU. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-10-30Merge tag 'armsoc-soc' of ↵Linus Torvalds14-95/+132
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "A couple of platforms change hands in the MAINTAINERS file: - Linus Walleij lists himself for the ARM Reference platforms: versatile, vexpress, integrator and realview. He has been the main contributor for these for a while, and makes it official now. - Vladimir Zapolskiy takes over the LPC18xx platform from Joachim Eastwood - Manivannan Sadhasivam becomes a secondary maintainer for the Actions Semi machines - Nicolas Ferre lists updates the MAINTAINER listing for the AT91 platform: Ludovic Desroches is now a co-maintainer for the platform, and several other people (Claudiu Beznea, Cristian Birsan, Eugen Hristev, Codrin Ciubotariu) take over individual device drivers. Thanks everyone for working on this, and welcome to the new maintainers! The "virt" platform on qemy or kvm can now be used in big-endian mode without additional tricks, thanks to Jason Donenfeld. Once again, we gain support for another NXP i.MX6 variant, this time it's the i.MX 6ULZ 32-bit single-core version. On arm64, we add support for two SoCs from Renesas: RZ/G2E (r8a774c0) and RZ/G2M (r8a774a1). These are described as microcontrollers on the manufacturer website, but appear to be rather powerful. The RZ/G2M is used on the reference board for the CIP Super Long Term Support (SLTS) Linux Kernels" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) MAINTAINERS: Assign myself as a maintainer of ARM/LPC18XX architecture arm64: exynos: Enable generic power domain support MAINTAINERS: remove non-exsiting email address of Baoyou MAINTAINERS: fix pattern in ARM/Synaptics berlin SoC section MAINTAINERS: Drop dt-bindings/genpd/k2g.h ARM: samsung: Limit SAMSUNG_PM_CHECK config option to non-Exynos platforms arm64: actions: Enable PINCTRL in platforms Kconfig MAINTAINERS: Add entry for Actions Semi Owl SoCs DMA driver MAINTAINERS: Add entry for Actions Semiconductor Owl I2C driver MAINTAINERS: Update clock binding entry for Actions Semi Owl SoCs ARM: imx: add i.mx6ulz msl support ARM: Assume maintainership of ARM reference designs ARM: support big-endian for the virt architecture MAINTAINERS: sdhci: move the Microchip entry to proper location MAINTAINERS: move former ATMEL entries to proper MICROCHIP location MAINTAINERS: remove the / ATMEL string from MICROCHIP entries MAINTAINERS: iio: add co-maintainer to SAMA5D2-compatible ADC driver MAINTAINERS: pwm: add entry for Microchip pwm driver MAINTAINERS: dmaengine: add files to Microchip dma entry MAINTAINERS: USB: change maintainer for Microchip USBA gadget driver ...
2018-10-30Merge tag 'armsoc-drivers' of ↵Linus Torvalds3-0/+34
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "The most noteworthy SoC driver changes this time include: - The TEE subsystem gains an in-kernel interface to access the TEE from device drivers. - The reset controller subsystem gains a driver for the Qualcomm Snapdragon 845 Power Domain Controller. - The Xilinx Zynq platform now has a firmware interface for its platform management unit. This contains a firmware "ioctl" interface that was a little controversial at first, but the version we merged solved that by not exposing arbitrary firmware calls to user space. - The Amlogic Meson platform gains a "canvas" driver that is used for video processing and shared between different high-level drivers. The rest is more of the usual, mostly related to SoC specific power management support and core drivers in drivers/soc: - Several Renesas SoCs (RZ/G1N, RZ/G2M, R-Car V3M, RZ/A2M) gain new features related to power and reset control. - The Mediatek mt8183 and mt6765 SoC platforms gain support for their respective power management chips. - A new driver for NXP i.MX8, which need a firmware interface for power management. - The SCPI firmware interface now contains support estimating power usage of performance states - The NVIDIA Tegra "pmc" driver gains a few new features, in particular a pinctrl interface for configuring the pads. - Lots of small changes for Qualcomm, in particular the "smem" device driver. - Some cleanups for the TI OMAP series related to their sysc controller. Additional cleanups and bugfixes in SoC specific drivers include the Meson, Keystone, NXP, AT91, Sunxi, Actions, and Tegra platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (129 commits) firmware: tegra: bpmp: Implement suspend/resume support drivers: clk: Add ZynqMP clock driver dt-bindings: clock: Add bindings for ZynqMP clock driver firmware: xilinx: Add zynqmp IOCTL API for device control Documentation: xilinx: Add documentation for eemi APIs MAINTAINERS: imx: include drivers/firmware/imx path firmware: imx: add misc svc support firmware: imx: add SCU firmware driver support reset: Fix potential use-after-free in __of_reset_control_get() dt-bindings: arm: fsl: add scu binding doc soc: fsl: qbman: add interrupt coalesce changing APIs soc: fsl: bman_portals: defer probe after bman's probe soc: fsl: qbman: Use last response to determine valid bit soc: fsl: qbman: Add 64 bit DMA addressing requirement to QBMan soc: fsl: qbman: replace CPU 0 with any online CPU in hotplug handlers soc: fsl: qbman: Check if CPU is offline when initializing portals reset: qcom: PDC Global (Power Domain Controller) reset controller dt-bindings: reset: Add PDC Global binding for SDM845 SoCs reset: Grammar s/more then once/more than once/ bus: ti-sysc: Just use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS ...
2018-09-28ARM: shmobile: use for_each_of_cpu_node iteratorRob Herring3-15/+5
Use the for_each_of_cpu_node iterator to iterate over cpu nodes. This has the side effect of defaulting to iterating using "cpu" node names in preference to the deprecated (for FDT) device_type == "cpu". Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Russell King <linux@armlinux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Rob Herring <robh@kernel.org>
2018-09-19ARM: shmobile: Rework the PMIC IRQ line quirkMarek Vasut1-29/+110
Rather than hard-coding the quirk topology, which stopped scaling, parse the information from DT. The code looks for all compatible PMICs -- da9063 and da9210 -- and checks if their IRQ line is tied to the same pin. If so, the code sends a matching sequence to the PMIC to deassert the IRQ. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> (on Koelsch) Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-17ARM: shmobile: r8a7744: Basic SoC supportBiju Das2-0/+7
Add minimal support for the RZ/G1N (R8A7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11ARM: shmobile: convert to SPDX identifiersKuninori Morimoto11-59/+14
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-30ARM: shmobile: Convert to using %pOFn instead of device_node.nameRob Herring1-1/+1
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-30ARM: shmobile: Remove the ARCH_SHMOBILE Kconfig symbolGeert Uytterhoeven1-4/+0
All drivers for Renesas ARM SoCs have gained proper ARCH_RENESAS platform dependencies. Hence finish the conversion from ARCH_SHMOBILE to ARCH_RENESAS for Renesas 32-bit ARM SoCs, as started by commit 9b5ba0df4ea4f940 ("ARM: shmobile: Introduce ARCH_RENESAS"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27ARM: shmobile: Add basic RZ/A2 SoC supportChris Brandt3-0/+34
Add the RZ/A2 SoC to the Renesas SoC collection. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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