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2014-05-08ARM: OMAP2+: raw read and write endian fixVictor Kamensky1-3/+3
All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-02-01ARM: OMAP4+: move errata initialization to omap4_pm_init_earlyNishanth Menon1-5/+1
Move all OMAP4 PM errata initializations to centralized location in omap4_pm_init_early. This allows for users to utilize the erratas in various submodules as needed. Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-10ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ registerR Sricharan1-0/+7
The realtime counter called master counter, produces the count used by the private timer peripherals in the MPU_CLUSTER. The CNTFRQ per cpu register is used to denote the frequency of the counter. Currently the frequency value is passed from the DT file, but this is not scalable when we have other non-DT guest OS. This register must be set to the right value by the secure rom code. Setting this register helps in propagating the right frequency value across OSes. More discussions and the reason for adding this in a non-DT way can be seen from below. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html So configuring this secure register for all the cpus here. Cc: Nishanth Menon <nm@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-09-18ARM: OMAP4 SMP: Corrected a typo fucntions to functionsAnoop Thomas Mathew1-1/+1
Corrected the functions spelling mistake in the OMAP4 SMP source file. Signed-off-by: Anoop Thomas Mathew <atm@profoundis.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-07-15arm: delete __cpuinit/__CPUINIT usage from all ARM usersPaul Gortmaker1-2/+2
The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. This removes all the ARM uses of the __cpuinit macros from C code, and all __CPUINIT from assembly code. It also had two ".previous" section statements that were paired off against __CPUINIT (aka .section ".cpuinit.text") that also get removed here. [1] https://lkml.org/lkml/2013/5/20/589 Cc: Russell King <linux@arm.linux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2013-05-16Merge tag 'omap-pm-v3.10/cleanup/pm' of ↵Tony Lindgren1-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-v3.11/pm OMAP PM cleanups for v3.10
2013-05-03Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds1-1/+1
Pull ARM updates from Russell King: "The major items included in here are: - MCPM, multi-cluster power management, part of the infrastructure required for ARMs big.LITTLE support. - A rework of the ARM KVM code to allow re-use by ARM64. - Error handling cleanups of the IS_ERR_OR_NULL() madness and fixes of that stuff for arch/arm - Preparatory patches for Cortex-M3 support from Uwe Kleine-König. There is also a set of three patches in here from Hugh/Catalin to address freeing of inappropriate page tables on LPAE. You already have these from akpm, but they were already part of my tree at the time he sent them, so unfortunately they'll end up with duplicate commits" * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (77 commits) ARM: EXYNOS: remove unnecessary use of IS_ERR_VALUE() ARM: IMX: remove unnecessary use of IS_ERR_VALUE() ARM: OMAP: use consistent error checking ARM: cleanup: OMAP hwmod error checking ARM: 7709/1: mcpm: Add explicit AFLAGS to support v6/v7 multiplatform kernels ARM: 7700/2: Make cpu_init() notrace ARM: 7702/1: Set the page table freeing ceiling to TASK_SIZE ARM: 7701/1: mm: Allow arch code to control the user page table ceiling ARM: 7703/1: Disable preemption in broadcast_tlb*_a15_erratum() ARM: mcpm: provide an interface to set the SMP ops at run time ARM: mcpm: generic SMP secondary bringup and hotplug support ARM: mcpm_head.S: vlock-based first man election ARM: mcpm: Add baremetal voting mutexes ARM: mcpm: introduce helpers for platform coherency exit/setup ARM: mcpm: introduce the CPU/cluster power API ARM: multi-cluster PM: secondary kernel entry code ARM: cacheflush: add synchronization helpers for mixed cache state accesses ARM: cpu hotplug: remove majority of cache flushing from platforms ARM: smp: flush L1 cache in cpu_die() ARM: tegra: remove tegra specific cpu_disable() ...
2013-04-09ARM: OMAP4+: Make secondary_startup function name more consistentSantosh Shilimkar1-3/+3
Current code has rather inconsistent function names for 'secondary_startup' routines. Update it to make it more consistent. Suggested by Kevin Hilman as part of OMAP5 PM patch review. Cc: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-04-09Merge tag 'omap-for-v3.10/fixes-pm-signed' of ↵Arnd Bergmann1-2/+10
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup From Tony Lindgren <tony@atomide.com>: Non-critical PM fix via Kevin Hilman <khilman@linaro.org>: OMAP PM fixes for v3.10 Note that this has a dependency to omap-for-v3.10/cleanup-v2-signed. * tag 'omap-for-v3.10/fixes-pm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method Signed-off-by: Arnd Bergmann <arnd@arndb.de<
2013-04-08Merge tag 'omap-for-v3.10/cleanup-v2-signed' of ↵Arnd Bergmann1-37/+20
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup From Tony Lindgren <tony@atomide.com>: Clean up related changes for v3.10 merge window. Mostly clock and PM related with removal of now unused DMA channel definitions. The clock change to use SoC specific lists will make it a little bit easier to add support for new SoCs variants without having to patch all over the place. * tag 'omap-for-v3.10/cleanup-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP4: Fix the init code to have OMAP4460 errata available in DT build ARM: OMAP4: PM: Now remove L4 per clockdomain static depedency with MPU ARM: OMAP4: PM: Remove L4 wakeup depedency with MPU since errata fix exist now ARM: OMAP4+: Move the CPU wakeup prepare code under smp_prepare_cpus() ARM: OMAP4+: Remove out of placed smp_wmb() in secondary wakeup code ARM: OMAP4+: Remove un-necessary cacheflush in secondary CPU boot path ARM: OMAP4+: Remove the un-necessary cache flush from hotplug code ARM: OMAP2+: PM: Remove bogus fiq_[enable/disable] tuple ARM: OMAP4+: Use common scratchpad SAR RAM offsets for all architectures ARM: OMAP2+: Remove unused DMA channel definitions ARM: OMAP1: Remove unused DMA channel definitions ARM: OMAP2+: clock data: Remove CK_* flags Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-06ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup ↵Santosh Shilimkar1-2/+10
method While waking up CPU from off state using clock domain force wakeup, restore the CPU power state to ON state before putting CPU clock domain under hardware control. Otherwise CPU wakeup might fail. The change is recommended for all OMAP4+ devices though the PRCM weakness was observed on OMAP5 devices first. As a result of weakness, lock-up is observed inside the hardware state machine of local CPU PRCM and results are UN-predictable as per designers. In software testing, we have seen hard-locks most of the time where system gets frozen. With power domain state restored, system behaves correctly. So update the code accordingly. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-03-28ARM: OMAP4+: Move the CPU wakeup prepare code under smp_prepare_cpus()Santosh Shilimkar1-31/+20
Move the secondary CPU wakeup prepare code under smp_prepare_cpus() where it belongs. It was remainder of the pen release code which was borrowed from ARM code initially. While at it drop the un-necessary sev() and barrier which was under prepare code. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-03-28ARM: OMAP4+: Remove out of placed smp_wmb() in secondary wakeup codeSantosh Shilimkar1-2/+0
The smp_wmb() here is out of placed and redundant. So remove it. It is a left over of the pen_release cleanup mostly. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-03-28ARM: OMAP4+: Remove un-necessary cacheflush in secondary CPU boot pathSantosh Shilimkar1-4/+0
This was borrowed from ARM versatile code with pen_release mechanism but since OMAP uses hardware register based synchronisation, pen_release stuff was dropped. Unfortunately the cacheflush wasn't dropped along with it. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-03-26irqchip: gic: Perform the gic_secondary_init() call via CPU notifierCatalin Marinas1-7/+0
All the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Tested-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Barry Song <baohua.song@csr.com>
2013-03-09Merge branch 'for-next' of git://git.pengutronix.de/git/ukl/linux into ↵Russell King1-1/+1
devel-stable Conflicts: arch/arm/include/asm/cputype.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-06Merge tag 'tegra-for-3.9-soc-t114' of ↵Olof Johansson1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stepen Warren: ARM: tegra: add Tegra114 SoC support This pull request adds initial support for the Tegra114 SoC, which integrates a quad-core ARM Cortex-A15 CPU. I'm proud to observe that we posted the initial versions of these patches before the final official announcement of this chip. These patches are enough to boot with a UART-based console, support the Dalmore and Pluto reference/evaluation boards, instantiate the GPIO and pinctrl drivers, and enable a cpuidle state. As yet, no clocks or storage devices are supported, but patches for those will follow shortly. This pull request is based on (most of) the previous pull request with tag tegra-for-3.9-soc-cpuidle, followed by a merge of the previous pull request with tag tegra-for-3.9-scu-base-rework. * tag 'tegra-for-3.9-soc-t114' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (24 commits) ARM: DT: tegra114: add pinmux DT entry ARM: DT: tegra114: add GPIO DT entry ARM: tegra114: select PINCTRL for Tegra114 SoC ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE support ARM: tegra: Add SMMU entry to Tegra114 DT ARM: tegra: add AHB entry to Tegra114 DT ARM: tegra: Add initial support for Tegra114 SoC. ARM: dt: tegra114: Add new board, Pluto ARM: dt: tegra114: Add new board, Dalmore ARM: dt: tegra114: Add new SoC base, Tegra114 SoC ARM: tegra: fuse: Add chip ID Tegra114 0x35 ARM: OMAP: Make use of available scu_a9_get_base() interface ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9 ARM: Add API to detect SCU base address from CP15 ARM: tegra: Use DT /cpu node to detect number of CPU core ARM: tegra: Add CPU nodes to Tegra30 device tree ARM: tegra: Add CPU nodes to Tegra20 device tree ARM: perf: simplify __hw_perf_event_init err handling ARM: perf: remove unnecessary checks for idx < 0 ARM: perf: handle armpmu_register failing ... Signed-off-by: Olof Johansson <olof@lixom.net> Remove/add conflict in arch/arm/mach-tegra/common.c resolved. Remove/remove conflict in arch/arm/mach-tegra/platsmp.c. Leave the empty stub function for now since removing it in the merge commit is confusing; will be cleaned up in a separate commit. # # It looks like you may be committing a merge. # If this is not correct, please remove the file # .git/MERGE_HEAD # and try again.
2013-02-01ARM: use read_cpuid_id() instead of read_cpuid(CPUID_ID)Uwe Kleine-König1-1/+1
Both calls are identical currently. This patch prepares to deprecate read_cpuid on machines without cp15. Also move an unconditional usage of read_cpuid_cachetype to a more local scope as read_cpuid_cachetype uses read_cpuid, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Message-Id: 1359646587-1788-1-git-send-email-u.kleine-koenig@pengutronix.de
2013-01-28ARM: OMAP: Make use of available scu_a9_get_base() interfaceSantosh Shilimkar1-1/+1
Drop the define and make use of scu_a9_get_base() which reads the physical address of SCU from CP15 register. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-12irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.hRob Herring1-1/+1
Now that we have GIC moved to drivers/irqchip and all GIC DT init for platforms using irqchip_init, move gic.h and update the remaining includes. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Anton Vorontsov <avorontsov@mvista.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Samuel Ortiz <sameo@linux.intel.com>
2013-01-10ARM: GIC: remove direct use of gic_raise_softirqRob Herring1-3/+1
In preparation of moving gic code to drivers/irqchip, remove the direct platform dependencies on gic_raise_softirq. Move the setup of smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask function to trigger wake-up IPIs. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Stephen Warren <swarren@nvidia.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net>
2012-11-15ARM: OMAP4: PM: fix errata handling when CONFIG_PM=nKevin Hilman1-0/+2
commit c9621844 (ARM: OMAP4: PM: add errata support) introduced errata handling for OMAP4, but was broken when CONFIG_PM=n. When CONFIG_PM=n, pm44xx.c is not compiled, yet that is where pm44xx_errata is defined. However, these errata are needed for the SMP boot/hotplug case also, and are primarily used in omap-smp.c. Move the definition of pm44xx_errata to omap-smp.c so that it's available even in the CONFIG_PM=n case. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-11-06ARM: OMAP4: retrigger localtimers after re-enabling gicColin Cross1-1/+12
'Workaround for ROM bug because of CA9 r2pX gic control' register change disables the gic distributor while the secondary cpu is being booted. If a localtimer interrupt on the primary cpu occurs when the distributor is turned off, the interrupt is lost, and the localtimer never fires again. Make the primary cpu wait for the secondary cpu to reenable the gic distributor (with interrupts off for safety), and then check if the pending bit is set in the localtimer but not the gic. If so, ack it in the localtimer, and reset the timer with the minimum timeout to trigger a new timer interrupt. Signed-off-by: Colin Cross <ccross@android.com> [s-jan@ti.com: adapted to k3.4 + validated functionality] Signed-off-by: Sebastien Jan <s-jan@ti.com> [t-kristo@ti.com: dropped generic ARM kernel exports from the code, rebased to mainline] Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-11-06ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control ↵Santosh Shilimkar1-1/+27
register change. On OMAP4+ devices, GIC register context is lost when MPUSS hits the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code gets executed and one of the steps in it is to restore the saved context of the GIC. The ROM Code GIC distributor restoration is split in two parts: CPU specific register done by each CPU and common register done by only one CPU. Below is the abstract flow. ............................................................... - MPUSS in OSWR state. - CPU0 wakes up on the event(interrupt) and start executing ROM code. [..] - CPU0 executes "GIC Restoration:" [...] - CPU0 swicthes to non-secure mode and jumps to OS resume code. [...] - CPU0 is online in OS - CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1 - CPU0 wakes up CPU1 with clock-domain force wakeup method. - CPU0 continues it's execution. [..] - CPU1 wakes up and start executing ROM code. [..] - CPU1 executes "GIC Restoration:" [..] - CPU1 swicthes to non-secure mode and jumps to OS resume code. [...] - CPU1 is online in OS and start executing. [...] - GIC Restoration: /* Common routine for HS and GP devices */ { if (GICD != 1) { /* This will be true in OSWR state */ if (GIC_SAR_BACKUP_STATE == SAVED) - CPU restores GIC distributor else - reconfigure GIC distributor to boot values. GICD.Enable secure = 1 } if (GIC_SAR_BACKUP_STATE == SAVED) - CPU restore its GIC CPU interface registers if saved. else - reconfigure its GIC CPU interface registers to boot values. } ............................................................... So as mentioned in the flow, GICD != 1 condition decides how the GIC registers are handled in ROM code wakeup path from OSWR. As evident from the flow, ROM code relies on the entire GICD register value and not specific register bits. The assumption was valid till CortexA9 r1pX version since there was only one banked bit to control secure and non-secure GICD. Secure view which ROM code sees: bit 0 == Enable Non-secure Non-secure view which HLOS sees: bit 0 == Enable secure But GICD register has changed between CortexA9 r1pX and r2pX. On r2pX GICD register is composed of 2 bits. Secure view which ROM code sees: bit 1 == Enable Non-secure bit 0 == Enable secure Non-secure view which HLOS sees: bit 0 == Enable Non-secure Hence on OMAP4460(r2pX) devices, if you go through the above flow again during CPU1 wakeup, GICD == 3 and hence ROM code fails to understand the real wakeup power state and reconfigures GIC distributor to boot values. This is nasty since you loose the entire interrupt controller context in a live system. The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path. Since ROM code can't be fixed on OMAP4460 devices, a work around needs to be implemented. As evident from the flow, as long as CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue won't happen. Below is the flow with the work-around. ............................................................... - MPUSS in OSWR state. - CPU0 wakes up on the event(interrupt) and start executing ROM code. [..] - CPU0 executes "GIC Restoration:" [..] - CPU0 swicthes to non-secure mode and jumps to OS resume code. [..] - CPU0 is online in OS. - CPU0 does GICD.Enable Non-secure = 0 - CPU0 wakes up CPU1 with clock domain force wakeup method. - CPU0 waits for GICD.Enable Non-secure = 1 - CPU0 coninues it's execution. [..] - CPU1 wakes up and start executing ROM code. [..] - CPU1 executes "GIC Restoration:" [..] - CPU1 swicthes to non-secure mode and jumps to OS resume code. [..] - CPU1 is online in OS - CPU1 does GICD.Enable Non-secure = 1 - CPU1 start executing [...] ............................................................... With this procedure, the GIC configuration done between the CPU0 wakeup and CPU1 wakeup will not be lost but during this short windows, the CPU0 will not receive interrupts. The BUG is applicable to only OMAP4460(r2pX) devices. OMAP4470 (also r2pX) is not affected by this bug because ROM code has been fixed. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-09-22Merge branch 'multiplatform/smp_ops' into next/multiplatformOlof Johansson1-4/+14
* multiplatform/smp_ops: ARM: consolidate pen_release instead of having per platform definitions ARM: smp: Make SMP operations mandatory ARM: SoC: convert spear13xx to SMP operations ARM: SoC: convert imx6q to SMP operations ARM: SoC: convert highbank to SMP operations ARM: SoC: convert shmobile SMP to SMP operations ARM: SoC: convert ux500 to SMP operations ARM: SoC: convert MSM to SMP operations ARM: SoC: convert Exynos4 to SMP operations ARM: SoC: convert Tegra to SMP operations ARM: SoC: convert OMAP4 to SMP operations ARM: SoC: convert VExpress/RealView to SMP operations ARM: SoC: add per-platform SMP operations Conflicts due to file moves or removals in: arch/arm/mach-msm/board-msm8960.c arch/arm/mach-msm/board-msm8x60.c arch/arm/mach-tegra/board-harmony.c arch/arm/mach-tegra/board-trimslice.c Conflicts due to board file cleanup: arch/arm/mach-tegra/board-paz00.c Conflicts due to cpu hotplug addition: arch/arm/mach-tegra/hotplug.c Signed-off-by: Olof Johansson <olof@lixom.net>
2012-09-21ARM: OMAP2+: Make omap-wakeupgen.h localTony Lindgren1-1/+1
This can be local to mach-omap2. Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-09-21ARM: OMAP2+: Make omap-secure.h localTony Lindgren1-1/+1
This can be local to mach-omap2. Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-09-13ARM: SoC: convert OMAP4 to SMP operationsMarc Zyngier1-4/+14
Convert OMAP4 to use struct smp_operations to provide its SMP and CPU hotplug operations. Tested on both Panda and IGEPv2 (MULTI_OMAP kernel) Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-09-13ARM: OMAP: Split plat/hardware.h, use local soc.h for omap2+Tony Lindgren1-1/+1
As the plat and mach includes need to disappear for single zImage work, we need to remove plat/hardware.h. Do this by splitting plat/hardware.h into omap1 and omap2+ specific files. The old plat/hardware.h already has omap1 only defines, so it gets moved to mach/hardware.h for omap1. For omap2+, we use the local soc.h that for now just includes the related SoC headers to keep this patch more readable. Note that the local soc.h still includes plat/cpu.h that can be dealt with in later patches. Let's also include plat/serial.h from common.h for all the board-*.c files. This allows making the include files local later on without patching these files again. Note that only minimal changes are done in this patch for the drivers/watchdog/omap_wdt.c driver to keep things compiling. Further patches are needed to eventually remove cpu_is_omap usage in the drivers. Also only minimal changes are done to sound/soc/omap/* to remove the unneeded includes and to define OMAP44XX_MCPDM_L3_BASE locally so there's no need to include omap44xx.h. While at it, also sort some of the includes in the standard way. Cc: linux-watchdog@vger.kernel.org Cc: alsa-devel@alsa-project.org Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jarkko Nikula <jarkko.nikula@bitmer.com> Cc: Liam Girdwood <lrg@ti.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-07-28Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds1-1/+1
Pull ARM updates from Russell King: "First ARM push of this merge window, post me coming back from holiday. This is what has been in linux-next for the last few weeks. Not much to say which isn't described by the commit summaries." * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (32 commits) ARM: 7463/1: topology: Update cpu_power according to DT information ARM: 7462/1: topology: factorize the update of sibling masks ARM: 7461/1: topology: Add arch_scale_freq_power function ARM: 7456/1: ptrace: provide separate functions for tracing syscall {entry,exit} ARM: 7455/1: audit: move syscall auditing until after ptrace SIGTRAP handling ARM: 7454/1: entry: don't bother with syscall tracing on ret_from_fork path ARM: 7453/1: audit: only allow syscall auditing for pure EABI userspace ARM: 7452/1: delay: allow timer-based delay implementation to be selected ARM: 7451/1: arch timer: implement read_current_timer and get_cycles ARM: 7450/1: dcache: select DCACHE_WORD_ACCESS for little-endian ARMv6+ CPUs ARM: 7449/1: use generic strnlen_user and strncpy_from_user functions ARM: 7448/1: perf: remove arm_perf_pmu_ids global enumeration ARM: 7447/1: rwlocks: remove unused branch labels from trylock routines ARM: 7446/1: spinlock: use ticket algorithm for ARMv6+ locking implementation ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process ARM: 7444/1: kernel: add arch-timer C3STOP feature ARM: 7460/1: remove asm/locks.h ARM: 7439/1: head.S: simplify initial page table mapping ARM: 7437/1: zImage: Allow DTB command line concatenation with ATAG_CMDLINE ARM: 7436/1: Do not map the vectors page as write-through on UP systems ...
2012-07-09ARM: OMAP: use SGI0 to wake secondary CPUsRussell King1-1/+1
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-07-09ARM: OMAP5: Add SMP supportSantosh Shilimkar1-12/+23
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths are runtime checked using cpu id Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2012-07-09ARM: OMAP5: Add the WakeupGen IP updatesSantosh Shilimkar1-2/+17
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5. - Additional 32 interrupt support is added w.r.t OMAP4 design. - The AUX CORE boot registers are now made accessible from non-secure SW. - SAR offset are changed and PTMSYNC* registers are removed from SAR. Patch updates the WakeupGen code accordingly. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2012-02-24ARM: OMAP2+: Move most of plat/io.h into local iomap.hTony Lindgren1-1/+2
There's no need to have these defines in plat/io.h. Note that we now need to ifdef omap_read/write calls as they will be available for omap1 only. While at it, clean up the includes to group them like they typically are grouped. Signed-off-by: Tony Lindgren <tony@atomide.com>
2011-12-08ARM: OMAP4: PM: CPU1 wakeup workaround from Low power modesSantosh Shilimkar1-0/+27
The SGI(Software Generated Interrupts) are not wakeup capable from low power states. This is known limitation on OMAP4 and needs to be worked around by using software forced clockdomain wake-up. CPU0 forces the CPU1 clockdomain to software force wakeup. More details can be found in OMAP4430 TRM - Version J Section : 4.3.4.2 Power States of CPU0 and CPU1 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-12-08ARM: OMAP4: PM: Add CPUX OFF mode supportSantosh Shilimkar1-0/+13
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch retention (CSWR) is not supported by hardware design. The CPUx OFF mode isn't supported on OMAP4430 ES1.0 CPUx sleep code is common for hotplug, suspend and CPUilde. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-12-08ARM: OMAP4: Export omap4_get_base*() rather than global address pointersSantosh Shilimkar1-0/+5
This patch exports APIs to get base address for GIC distributor, CPU interface, SCU and PL310 L2 Cache which are used in OMAP4 PM code. This was suggested by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-11-17ARM: 7159/1: OMAP: Introduce local common.h filesTony Lindgren1-1/+2
As suggested by Russell King - ARM Linux <linux@arm.linux.org.uk>, there's no need to keep local prototypes in non-local headers. Add mach-omap1/common.h and mach-omap2/common.h and move the local prototypes there from plat/common.h and mach/omap4-common.h. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-11-02Merge branch 'next/cleanup2' of git://git.linaro.org/people/arnd/arm-socLinus Torvalds1-2/+5
* 'next/cleanup2' of git://git.linaro.org/people/arnd/arm-soc: (31 commits) ARM: OMAP: Warn if omap_ioremap is called before SoC detection ARM: OMAP: Move set_globals initialization to happen in init_early ARM: OMAP: Map SRAM later on with ioremap_exec() ARM: OMAP: Remove calls to SRAM allocations for framebuffer ARM: OMAP: Avoid cpu_is_omapxxxx usage until map_io is done ARM: OMAP1: Use generic map_io, init_early and init_irq arm/dts: OMAP3+: Add mpu, dsp and iva nodes arm/dts: OMAP4: Add a main ocp entry bound to l3-noc driver ARM: OMAP2+: l3-noc: Add support for device-tree ARM: OMAP2+: board-generic: Add i2c static init ARM: OMAP2+: board-generic: Add DT support to generic board arm/dts: Add support for OMAP3 Beagle board arm/dts: Add initial device tree support for OMAP3 SoC arm/dts: Add support for OMAP4 SDP board arm/dts: Add support for OMAP4 PandaBoard arm/dts: Add initial device tree support for OMAP4 SoC ARM: OMAP: omap_device: Add a method to build an omap_device from a DT node ARM: OMAP: omap_device: Add omap_device_[alloc|delete] for DT integration of: Add helpers to get one string in multiple strings property ARM: OMAP2+: devices: Remove all omap_device_pm_latency structures ... Fix up trivial header file conflicts in arch/arm/mach-omap2/board-generic.c
2011-10-21ARM: smp: fix clipping of number of CPUsRussell King1-6/+4
Rather than clipping the number of CPUs using the compile-time NR_CPUS constant, use the runtime nr_cpu_ids value instead. This allows the nr_cpus command line option to work as expected. Cc: <stable@kernel.org> Reported-by: Mark Salter <msalter@redhat.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-20ARM: OMAP: Move set_globals initialization to happen in init_earlyTony Lindgren1-2/+5
Otherwise we can't do generic map_io as we currently rely on static mappings that work only because of arch_ioremap. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2011-07-07ARM: 6993/1: platsmp: Allow secondary cpu hotplug with maxcpus=1Stephen Boyd1-8/+0
If an ARM system has multiple cpus in the same socket and the kernel is booted with maxcpus=1, secondary cpus are possible but not present due to how platform_smp_prepare_cpus() is called. Since most typical ARM processors don't actually support physical hotplug, initialize the present map to be equal to the possible map in generic ARM SMP code. Also, always call platform_smp_prepare_cpus() as long as max_cpus is non-zero (0 means no SMP) to allow platform code to do any SMP setup. After applying this patch it's possible to boot an ARM system with maxcpus=1 on the command line and then hotplug in secondary cpus via sysfs. This is more in line with how x86 does things. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-23ARM: consolidate SMP cross call implementationRussell King1-1/+4
Rather than having each platform class provide a mach/smp.h header for smp_cross_call(), arrange for them to register the function with the core ARM SMP code instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-07Merge branch 'misc' into develRussell King1-51/+15
Conflicts: arch/arm/Kconfig arch/arm/common/Makefile arch/arm/kernel/Makefile arch/arm/kernel/smp.c
2010-12-20ARM: SMP: consolidate trace_hardirqs_off() into common SMP codeRussell King1-2/+0
All platforms call trace_hardirqs_off() in their secondary startup code, so move this into the core SMP code - it doesn't need to be in the per-platform code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20ARM: SMP: consolidate the common parts of smp_prepare_cpus()Russell King1-26/+7
There is a certain amount of smp_prepare_cpus() which doesn't belong in the platform support code - that is, code which is invariant to the SMP implementation. Move this code into arch/arm/kernel/smp.c, and add a platform_ prefix to the original function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20ARM: SMP: get rid of get_core_count()Russell King1-11/+1
We don't need this small function as well as scu_get_core_count() Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20ARM: SMP: Clean up ncores sanity checksRussell King1-6/+0
scu_get_core_count() never returns zero cores, so we don't need to check and correct if ncores is zero. Tegra was missing the check against NR_CPUS, leading to a potential bitfield overflow if this becomes the case. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20ARM: SMP: move CPU number sanity checks to smp_init_cpus()Russell King1-10/+11
Ensure that the number of CPUs is sanity checked before setting the number of possible CPUs. This avoids any chance of overflowing the cpu_possible bitmap. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_initRussell King1-1/+1
We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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