kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Collapse)	Author	Files	Lines
2010-01-20	OMAP4: clocks: Fix the clksel_rate struct DPLL divs	Rajendra Nayak	1	-31/+31
	For all DPLL's the valid dividers are same as the values to be programmed in the register. 0 is an invalid value. The changes are generated by updating the script which autogenerates the file modifed in the patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-12-12	ARM: OMAP4: PM: Add init api for DPLL nodes	Rajendra Nayak	1	-0/+7
	An api at init for all dpll nodes seem to be needed to reparent the dpll clk node to its bypass clk in case the dpll is in bypass. If not done this causes sequencing issues at init during propogate_rate. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
2009-12-12	ARM: OMAP4: PM: OMAP4 clock tree and clkdev registration	Rajendra Nayak	1	-0/+2759
	This patch defines all the clock nodes in OMAP4430 platform. All the clock node structs and the clkdev table is autogenerated using a python script (gen_clock_tree.py) developed by Paul Walmsley, Benoit Cousson and Rajendra Nayak. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>