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2023-03-11ARM: imx: Call ida_simple_remove() for ida_simple_getAngus Chen1-12/+12
[ Upstream commit ebeb49f43c8952f12aa20f03f00d7009edc2d1c5 ] The function call ida_simple_get maybe fail,we should deal with it. And if ida_simple_get success ,it need to call ida_simple_remove also. BTW,devm_kasprintf can handle id is zero for consistency. Fixes: e76bdfd7403a ("ARM: imx: Added perf functionality to mmdc driver") Signed-off-by: Angus Chen <angus.chen@jaguarmicro.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-10-13ARM: imx6: disable the GIC CPU interface before calling stby-poweroff sequenceOleksij Rempel1-0/+2
[ Upstream commit 783f3db030563f7bcdfe2d26428af98ea1699a8e ] Any pending interrupt can prevent entering standby based power off state. To avoid it, disable the GIC CPU interface. Fixes: 8148d2136002 ("ARM: imx6: register pm_power_off handler if "fsl,pmic-stby-poweroff" is set") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-09-22ARM: imx: fix missing 3rd argument in macro imx_mmdc_perf_initColin Ian King1-1/+1
commit 20fb73911fec01f06592de1cdbca00b66602ebd7 upstream. The function imx_mmdc_perf_init recently had a 3rd argument added to it but the equivalent macro was not updated and is still the older 2 argument version. Fix this by adding in the missing 3rd argumement mmdc_ipg_clk. Fixes: f07ec8536580 ("ARM: imx: add missing clk_disable_unprepare()") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Nobuhiro Iwamatsu (CIP) <nobuhiro1.iwamatsu@toshiba.co.jp> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-09-22ARM: imx: add missing clk_disable_unprepare()Yang Yingliang1-3/+9
commit f07ec85365807b3939f32d0094a6dd5ce065d1b9 upstream. clock source is prepared and enabled by clk_prepare_enable() in probe function, but no disable or unprepare in remove and error path. Fixes: 9454a0caff6a ("ARM: imx: add mmdc ipg clock operation for mmdc") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Nobuhiro Iwamatsu (CIP) <nobuhiro1.iwamatsu@toshiba.co.jp> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-08-12ARM: imx: add mmdc ipg clock operation for mmdcAnson Huang1-0/+14
[ Upstream commit 9454a0caff6ac6d2a5ea17dd624dc13387bbfcd3 ] i.MX6 SoCs have MMDC ipg clock for registers access, to make sure MMDC registers access successfully, add optional clock enable for MMDC driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-08-12ARM: imx: add missing iounmap()Yang Yingliang1-1/+6
[ Upstream commit f9613aa07f16d6042e74208d1b40a6104d72964a ] Commit e76bdfd7403a ("ARM: imx: Added perf functionality to mmdc driver") introduced imx_mmdc_remove(), the mmdc_base need be unmapped in it if config PERF_EVENTS is enabled. If imx_mmdc_perf_init() fails, the mmdc_base also need be unmapped. Fixes: e76bdfd7403a ("ARM: imx: Added perf functionality to mmdc driver") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-28ARM: imx: pm-imx5: Fix references to imx5_cpu_suspend_infoJonathan Neuschäfer1-2/+2
[ Upstream commit 89b759469d525f4d5f9c29cd3b1f490311c67f85 ] The name of the struct, as defined in arch/arm/mach-imx/pm-imx5.c, is imx5_cpu_suspend_info. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-02-04ARM: imx: build suspend-imx6.S with arm instruction setMax Krummenacher1-0/+1
commit a88afa46b86ff461c89cc33fc3a45267fff053e8 upstream. When the kernel is configured to use the Thumb-2 instruction set "suspend-to-memory" fails to resume. Observed on a Colibri iMX6ULL (i.MX 6ULL) and Apalis iMX6 (i.MX 6Q). It looks like the CPU resumes unconditionally in ARM instruction mode and then chokes on the presented Thumb-2 code it should execute. Fix this by using the arm instruction set for all code in suspend-imx6.S. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Fixes: df595746fa69 ("ARM: imx: add suspend in ocram support for i.mx6q") Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-07-16ARM: imx6: add missing put_device() call in imx6q_suspend_init()yu kuai1-4/+6
[ Upstream commit 4845446036fc9c13f43b54a65c9b757c14f5141b ] if of_find_device_by_node() succeed, imx6q_suspend_init() doesn't have a corresponding put_device(). Thus add a jump target to fix the exception handling for this function implementation. Signed-off-by: yu kuai <yukuai3@huawei.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-07-01ARM: imx5: add missing put_device() call in imx_suspend_alloc_ocram()yu kuai1-2/+4
[ Upstream commit 586745f1598ccf71b0a5a6df2222dee0a865954e ] if of_find_device_by_node() succeed, imx_suspend_alloc_ocram() doesn't have a corresponding put_device(). Thus add a jump target to fix the exception handling for this function implementation. Fixes: 1579c7b9fe01 ("ARM: imx53: Set DDR pins to high impedance when in suspend to RAM.") Signed-off-by: yu kuai <yukuai3@huawei.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-04-29ARM: imx: provide v7_cpu_resume() only on ARM_CPU_SUSPEND=yAhmad Fatoum1-0/+2
commit f1baca8896ae18e12c45552a4c4ae2086aa7e02c upstream. 512a928affd5 ("ARM: imx: build v7_cpu_resume() unconditionally") introduced an unintended linker error for i.MX6 configurations that have ARM_CPU_SUSPEND=n which can happen if neither CONFIG_PM, CONFIG_CPU_IDLE, nor ARM_PSCI_FW are selected. Fix this by having v7_cpu_resume() compiled only when cpu_resume() it calls is available as well. The C declaration for the function remains unguarded to avoid future code inadvertently using a stub and introducing a regression to the bug the original commit fixed. Cc: <stable@vger.kernel.org> Fixes: 512a928affd5 ("ARM: imx: build v7_cpu_resume() unconditionally") Reported-by: Clemens Gruber <clemens.gruber@pqgruber.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Tested-by: Roland Hieber <rhi@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-11ARM: imx: build v7_cpu_resume() unconditionallyAhmad Fatoum4-16/+28
commit 512a928affd51c2dc631401e56ad5ee5d5dd68b6 upstream. This function is not only needed by the platform suspend code, but is also reused as the CPU resume function when the ARM cores can be powered down completely in deep idle, which is the case on i.MX6SX and i.MX6UL(L). Providing the static inline stub whenever CONFIG_SUSPEND is disabled means that those platforms will hang on resume from cpuidle if suspend is disabled. So there are two problems: - The static inline stub masks the linker error - The function is not available where needed Fix both by just building the function unconditionally, when CONFIG_SOC_IMX6 is enabled. The actual code is three instructions long, so it's arguably ok to just leave it in for all i.MX6 kernel configurations. Fixes: 05136f0897b5 ("ARM: imx: support arm power off in cpuidle for i.mx6sx") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-11-20ARM: imx6: register pm_power_off handler if "fsl,pmic-stby-poweroff" is setOleksij Rempel1-0/+25
[ Upstream commit 8148d2136002da2e2887caf6a07bbd9c033f14f3 ] One of the Freescale recommended sequences for power off with external PMIC is the following: ... 3. SoC is programming PMIC for power off when standby is asserted. 4. In CCM STOP mode, Standby is asserted, PMIC gates SoC supplies. See: http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdf page 5083 This patch implements step 4. of this sequence. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-06-25ARM: imx: cpuidle-imx6sx: Restrict the SW2ISO increase to i.MX6SXFabio Estevam1-1/+2
commit b25af2ff7c07bd19af74e3f64ff82e2880d13d81 upstream. Since commit 1e434b703248 ("ARM: imx: update the cpu power up timing setting on i.mx6sx") some characters loss is noticed on i.MX6ULL UART as reported by Christoph Niedermaier. The intention of such commit was to increase the SW2ISO field for i.MX6SX only, but since cpuidle-imx6sx is also used on i.MX6UL/i.MX6ULL this caused unintended side effects on other SoCs. Fix this problem by keeping the original SW2ISO value for i.MX6UL/i.MX6ULL and only increase SW2ISO in the i.MX6SX case. Cc: stable@vger.kernel.org Fixes: 1e434b703248 ("ARM: imx: update the cpu power up timing setting on i.mx6sx") Reported-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Tested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-04ARM: imx51: fix a leaked reference by adding missing of_node_putWen Yang1-0/+1
[ Upstream commit 0c17e83fe423467e3ccf0a02f99bd050a73bbeb4 ] The call to of_get_next_child returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./arch/arm/mach-imx/mach-imx51.c:64:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 57, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Cc: Russell King <linux@armlinux.org.uk> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin (Microsoft) <sashal@kernel.org>
2019-04-03ARM: imx6q: cpuidle: fix bug that CPU might not wake up at expected timeKohji Okuno1-17/+10
commit 91740fc8242b4f260cfa4d4536d8551804777fae upstream. In the current cpuidle implementation for i.MX6q, the CPU that sets 'WAIT_UNCLOCKED' and the CPU that returns to 'WAIT_CLOCKED' are always the same. While the CPU that sets 'WAIT_UNCLOCKED' is in IDLE state of "WAIT", if the other CPU wakes up and enters IDLE state of "WFI" istead of "WAIT", this CPU can not wake up at expired time. Because, in the case of "WFI", the CPU must be waked up by the local timer interrupt. But, while 'WAIT_UNCLOCKED' is set, the local timer is stopped, when all CPUs execute "wfi" instruction. As a result, the local timer interrupt is not fired. In this situation, this CPU will wake up by IRQ different from local timer. (e.g. broacast timer) So, this fix changes CPU to return to 'WAIT_CLOCKED'. Signed-off-by: Kohji Okuno <okuno.kohji@jp.panasonic.com> Fixes: e5f9dec8ff5f ("ARM: imx6q: support WAIT mode using cpuidle") Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-01-13ARM: imx: update the cpu power up timing setting on i.mx6sxAnson Huang1-1/+1
[ Upstream commit 1e434b703248580b7aaaf8a115d93e682f57d29f ] The sw2iso count should cover ARM LDO ramp-up time, the MAX ARM LDO ramp-up time may be up to more than 100us on some boards, this patch sets sw2iso to 0xf (~384us) which is the reset value, and it is much more safe to cover different boards, since we have observed that some customer boards failed with current setting of 0x2. Fixes: 05136f0897b5 ("ARM: imx: support arm power off in cpuidle for i.mx6sx") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2018-07-12ARM: mx5: Set the DBGEN bit in ARM_GPC registerFabio Estevam4-1/+48
On i.MX51/i.MX53 it is necessary to set the DBGEN bit in ARM_GPC register in order to turn on the debug clocks. The DBGEN bit of ARM_GPC register has the following description in the i.MX53 Reference Manual: "This allows the user to manually activate clocks within the debug system. This register bit directly controls the platform's dbgen_out output signal which connects to the DAP_SYS to enable all debug clocks. Once enabled, the clocks cannot be disabled except by asserting the disable_trace input of the DAP_SYS." Based on a previous patch from Sebastian Reichel. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-07-12ARM: imx51: Configure M4IF to avoid visual artifactsFabio Estevam1-1/+28
Configure the M4IF registers as per the vendor bootloader to avoid visual artifacts during video playback. This way we don't need to rely on the bootloader configuration for optimal IPU/VPU bus priorities. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Sergey Lapin <sergey.lapin@cogentembedded.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-07-11ARM: imx: call imx6sx_cpuidle_init() conditionally for 6sllArnd Bergmann1-2/+2
The imx6sl platform has two different cpuidle implementations, and fails to link if we only want one of the two: arch/arm/mach-imx/mach-imx6sl.o: In function `imx6sl_init_late': mach-imx6sl.c:(.init.text+0x12): undefined reference to `imx6sx_cpuidle_init' This makes the call into reference conditional on the configuration. Fixes: e7fa1fb39b11 ("ARM: imx: add cpu idle support for i.MX6SLL") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-07-11ARM: imx: fix i.MX6SLL buildArnd Bergmann1-2/+2
The i.MX6SLL cpuidle support reuses the i.MX6SX implementation, but the Makefile accidentally enables the i.MX6SL one as well, which then fails with a link error unless the kernel also enables the the i.MX6SL clock driver: arch/arm/mach-imx/cpuidle-imx6sl.o: In function `imx6sl_enter_wait': cpuidle-imx6sl.c:(.text+0x24): undefined reference to `imx6sl_set_wait_clk' This changes the two lines that were just modified again, hopefully getting every case right this time. Fixes: e7fa1fb39b11 ("ARM: imx: add cpu idle support for i.MX6SLL") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-07-11ARM: imx: flag failure of of_iomapNicholas Mc Guire1-0/+1
imx_set_aips is assuming that the address returned from of_iomap is valid which it probably is in the normal case - as the call site is void error propagation is not possible but never the less at least a WARN_ON() seems warranted here. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Fixes: commit e57e4ab5fc2e ("ARM: i.MX: allow disabling supervisor protect via DT") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-07-11ARM: i.MX31: remove rnga registration as a platform deviceVladimir Zapolskiy1-18/+0
On i.MX31 powered boards with OF support Security Random Number Generator Accelerator RNGA controller is initialized from device tree, its registration as a platform device is redundant and actually it is broken due to missing clock information: mxc_rnga mxc_rnga: Could not get rng_clk! mxc_rnga: probe of mxc_rnga failed with error -2 Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-07-03ARM: imx: Provide support for NXP i.MX7D Cortex-M4Oleksij Rempel3-13/+41
Cortex M4 part can be started from a boot loader or over Linux remoteproc framework. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-07-03ARM: imx: enable bus auto clock gating function for i.mx6sllAnson Huang1-2/+9
i.MX6SLL has HW bus auto clock gating function, enable it by default to save VDD_SOC_IN power, about 5% ~ 20% saved depends on different use cases. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19ARM: imx: remove i.MX6SLL support in i.MX6SL cpu idle driverAnson Huang1-5/+2
i.MX6SLL supports ARM power off in cpu idle, better to reuse i.MX6SX cpu idle driver instead of i.MX6SL which does NOT support ARM power off. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19ARM: imx: add cpu idle support for i.MX6SLLAnson Huang3-3/+7
i.MX6SLL supports cpu idle with ARM power gated, it can reuse i.MX6SX's cpu idle driver to support below 3 states of cpu idle: state0: WFI; state1: WAIT mode with ARM power on; state2: WAIT mode with ARM power off. L2_PGE in GPC_CNTR needs to be cleared to support state2 cpu idle. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19ARM: imx: add L2 page power control for GPCAnson Huang2-0/+15
Some platforms like i.MX6UL/i.MX6SLL have L2 page power control in GPC, it needs to be disabled if ARM is power gated and L2 is NOT flushed, add GPC interface to control it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19ARM: imx: add mem mode suspend for i.MX6SLLAnson Huang1-2/+22
Add mem mode suspend for i.MX6SLL, when linux kernel suspend, SoC will enter STOP mode, ARM core will be power gated and MMDC IO will be set to low power mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19ARM: imx: add standby mode suspend for i.MX6SLLAnson Huang1-1/+1
Add standby mode suspend for i.MX6SLL, when linux kernel suspend, SoC will enter STOP mode with ARM core power on. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-17ARM: imx: remove inexistant EPIT timer initClément Peron1-1/+0
i.MX EPIT timer has been removed but not the init function declaration. Signed-off-by: Clément Peron <clement.peron@devialet.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-05-02ARM: imx: select imx6sll pinctrl when imx6sll enabledBai Ping1-0/+1
select imx6sll pinctrl driver if imx6sll config is enabled. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-04-18ARM: imx: pcm037: use device properties for at24 eepromBartosz Golaszewski1-7/+6
We want to work towards phasing out the at24_platform_data structure. There are few users and its contents can be represented using generic device properties. Using device properties only will allow us to significantly simplify the at24 configuration code. Remove the at24_platform_data structure and replace it with an array of property entries. Specify the exact model instead of the "at24" wildcard and drop the byte_len/size property, as the model name already implies the EEPROM's size. Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-04-18ARM: imx: pca100: use device properties for at24 eepromBartosz Golaszewski1-7/+6
We want to work towards phasing out the at24_platform_data structure. There are few users and its contents can be represented using generic device properties. Using device properties only will allow us to significantly simplify the at24 configuration code. Remove the at24_platform_data structure and replace it with an array of property entries. Specify the exact model instead of the "at24" wildcard and drop the byte_len/size property, as the model name already implies the EEPROM's size. Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-04-18ARM: imx: pcm043: use device properties for at24 eepromBartosz Golaszewski1-7/+6
We want to work towards phasing out the at24_platform_data structure. There are few users and its contents can be represented using generic device properties. Using device properties only will allow us to significantly simplify the at24 configuration code. Remove the at24_platform_data structure and replace it with an array of property entries. Specify the exact model instead of the "at24" wildcard and drop the byte_len/size property, as the model name already implies the EEPROM's size. Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-04-18ARM: imx: vpr200: drop at24_platform_dataBartosz Golaszewski1-8/+1
The information contained in the platform data struct is redundant. Page size == 1 is the safe default assumed if no pagesize property is given. The EEPROM size can be indicated to the driver using the correct model name. Drop the at24_platform_data entirely. Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-04-18ARM: imx: Update spi_imx platform data to reflect current stateTrent Piepho5-58/+10
The docs for the spi_imx platform data still refer to a -32 offset used to specify a native chip select. This was removed in commit 602c8f4485cd ("spi: imx: fix use of native chip-selects with devicetree") and no longer works as documented. Update documentation. The macro MXC_SPI_CS() is no longer is needed. If a board uses all native chip selects, then it's not necessary to specify a chip select array at all, as all native is the default (this is how device-tree configured SPI masters work too). Most of the spi-imx platform data users have their chip select arrays removed by this patch. This patch also fixes a bug in mx31moboard introduced in the '602 commit. When that board was updated in commit 901f26bce64a ("ARM: imx: set correct chip_select in platform setup") to reflect the SPI change, only SPI bus 2 was updated and SPI bus 1 was left with non-sequential chip selects. The mc13783 spi device on bus 1 had its chip select updated as if it were on bus 2. CC: Sascha Hauer <kernel@pengutronix.de> CC: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Greg Ungerer <gerg@linux-m68k.org> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-04-06Merge tag 'armsoc-soc' of ↵Linus Torvalds11-289/+91
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "This release brings up a new platform based on the old ARM9 core: the Nuvoton NPCM is used as a baseboard management controller, competing with the better known ASpeed AST2xx series. Another important change is the addition of ARMv7-A based chips in mach-stm32. The older parts in this platform are ARMv7-M based microcontrollers, now they are expanding to general-purpose workloads. The other changes are the usual defconfig updates to enable additional drivers, lesser bugfixes. The largest updates as often are the ongoing OMAP cleanups, but we also have a number of changes for the older PXA and davinci platforms this time. For the Renesas shmobile/r-car platform, some new infrastructure is needed to make the watchdog work correctly. Supporting Multiprocessing on Allwinner A80 required a significant amount of new code, but is not doing anything unexpected" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (179 commits) arm: npcm: modify configuration for the NPCM7xx BMC. MAINTAINERS: update entry for ARM/berlin ARM: omap2: fix am43xx build without L2X0 ARM: davinci: da8xx: simplify CFGCHIP regmap_config ARM: davinci: da8xx: fix oops in USB PHY driver due to stack allocated platform_data ARM: multi_v7_defconfig: add NXP FlexCAN IP support ARM: multi_v7_defconfig: enable thermal driver for i.MX devices ARM: multi_v7_defconfig: add RN5T618 PMIC family support ARM: multi_v7_defconfig: add NXP graphics drivers ARM: multi_v7_defconfig: add GPMI NAND controller support ARM: multi_v7_defconfig: add OCOTP driver for NXP SoCs ARM: multi_v7_defconfig: configure I2C driver built-in arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and CONFIG_SNI_AVE ARM: imx: fix imx6sll-only build ARM: imx: select ARM_CPU_SUSPEND for CPU_IDLE as well ARM: mxs_defconfig: Re-sync defconfig ARM: imx_v4_v5_defconfig: Use the generic fsl-asoc-card driver ARM: imx_v4_v5_defconfig: Re-sync defconfig arm64: defconfig: enable stmmac ethernet to defconfig ARM: EXYNOS: Simplify code in coupled CPU idle hot path ...
2018-03-27ARM: imx: fix imx6sll-only buildArnd Bergmann1-0/+1
When selecting SOC_IMX6SLL but not SOC_IMX6SL, we get a link error: arch/arm/mach-imx/mach-imx6sl.o: In function `imx6sl_init_late': mach-imx6sl.c:(.init.text+0x14): undefined reference to `imx6sl_cpuidle_init' This adds the missing line to the Makefile to also build the cpuidle support that we need here. Fixes: dee5dee2a5b2 ("ARM: imx: Add basic msl support for imx6sll") Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-27ARM: imx: select ARM_CPU_SUSPEND for CPU_IDLE as wellArnd Bergmann1-1/+1
The cpuidle support calls cpu_suspend(), which is compiled conditionally, and fails to link unless something selects CONFIG_ARM_CPU_SUSPEND. arch/arm/mach-imx/cpuidle-imx6sx.o: In function `imx6sx_enter_wait': cpuidle-imx6sx.c:(.text+0x6c): undefined reference to `cpu_suspend' This adds an explicit select statement here. Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-16perf: Fix sibling iterationPeter Zijlstra1-1/+1
Mark noticed that the change to sibling_list changed some iteration semantics; because previously we used group_list as list entry, sibling events would always have an empty sibling_list. But because we now use sibling_list for both list head and list entry, siblings will report as having siblings. Fix this with a custom for_each_sibling_event() iterator. Fixes: 8343aae66167 ("perf/core: Remove perf_event::group_entry") Reported-by: Mark Rutland <mark.rutland@arm.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: vincent.weaver@maine.edu Cc: alexander.shishkin@linux.intel.com Cc: torvalds@linux-foundation.org Cc: alexey.budankov@linux.intel.com Cc: valery.cherepennikov@intel.com Cc: eranian@google.com Cc: acme@redhat.com Cc: linux-tip-commits@vger.kernel.org Cc: davidcc@google.com Cc: kan.liang@intel.com Cc: Dmitry.Prohorov@intel.com Cc: jolsa@redhat.com Link: https://lkml.kernel.org/r/20180315170129.GX4043@hirez.programming.kicks-ass.net
2018-03-12perf/core: Remove perf_event::group_entryPeter Zijlstra1-1/+1
Now that all the grouping is done with RB trees, we no longer need group_entry and can replace the whole thing with sibling_list. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexey Budankov <alexey.budankov@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: David Carrillo-Cisneros <davidcc@google.com> Cc: Dmitri Prokhorov <Dmitry.Prohorov@intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Valery Cherepennikov <valery.cherepennikov@intel.com> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-03-09ARM: imx: Add basic msl support for imx6sllBai Ping6-4/+30
Add basic MSL support for i.MX6SLL. The i.MX 6SoloLiteLite application processors are NXP's latest additions to a growing family of multimedia-focused products offering high-performance processing optimized for lowest power consumption. The i.MX 6SoloLiteLite processors feature NXP's advanced implementation of the ARM Cortex-A9 core, which can be interfaced with LPDDR3 and LPDDR2 DRAM memory devices. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-28ARM: imx: pm-imx6: Return the error directlyFabio Estevam1-5/+2
Simplify the error path by returning the error code directly rather than jumping to a label. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-28ARM: imx: avic: set low-power interrupt mask for imx25Martin Kaiser1-0/+37
imx25 contains two registers (LPIMR0 and 1) to define which interrupts are enabled in low-power mode. As of today, those two registers are configured to enable all interrupts. Before going to low-power mode, the AVIC's INTENABLEH and INTENABLEL registers are configured to enable only those interrupts which are used as wakeup sources. It turned out that this approach is not sufficient if we want the imx25 to go into stop mode during suspend-to-ram. (Stop mode is the low-power mode that consumes the least power. The peripheral master clock is switched off in this mode). For stop mode to work, the LPIMR0 and 1 registers have to be configured with the set of interrupts that are allowed in low-power mode. Fortunately, the bits in the LPIMR registers are assigned to the same interrupts as the bits in INTENABLEH and INTENABLEL. However, LPIMR uses 1 to mask an interrupt whereas the INTENABLE registers use 1 to enable an interrupt. This patch sets the LPIMR registers to the inverted bitmask of the INTENABLE registers during suspend and goes back to "all interrupts masked" when we wake up again. We also make this the default at startup. As far as I know, the other supported imx architectures have no similar mechanism. Since the LPIMR registers are part of the CCM module, we query the device tree for an imx25 ccm node in order to detect if we're running on imx25. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-12ARM: imx: Improve the soc revision calculation flowBai Ping1-37/+19
On our i.MX6 SOC, the DIGPROG register is used for representing the SOC ID and silicon revision. The revision has two part: MAJOR and MINOR. each is represented in 8 bits in the register. bits [15:8]: reflect the MAJOR part of the revision; bits [7:0]: reflect the MINOR part of the revision; In our linux kernel, the soc revision is represented in 8 bits. MAJOR part and MINOR each occupy 4 bits. previous method does NOT take care about the MAJOR part in DIGPROG register. So reformat the revision read from the HW to be compatible with the revision format used in kernel. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-12ARM: imx: add timer stop flag to ARM power off stateStefan Agner1-0/+1
When the CPU is in ARM power off state the ARM architected timers are stopped. The flag is already present in the higher power WAIT mode. This allows to use the ARM generic timer on i.MX 6UL/6ULL SoC. Without the flag the kernel freezes when the timer enters the first time ARM power off mode. Note: The default timer on i.MX6SX is the i.MX GPT timer which is not disabled during CPU idle. However, the timer is not affected by the CPUIDLE_FLAG_TIMER_STOP flag. The flag only affects CPU local timers. Cc: Anson Huang <anson.huang@nxp.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-12ARM: imx: Remove epit supportFabio Estevam3-242/+0
Currently there is no user of EPIT, so remove such unused code. If someone wants to add EPIT support back, then the person needs to create a proper support into drivers/clocksource/ and add device tree support, proper bindings, etc. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-12-26ARM: imx: remove unused imx3 pm definitionsMartin Kaiser1-9/+0
Remove the defintion of mx3_cpu_lp_set(), this function is not implemented anywhere. Remove then mx3_cpu_pwr_mode enum as well, it was used only as parameter of mx3_cpu_lp_set(). Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-12-26ARM: imx: don't abort MMDC probe if power saving status doesn't matchLucas Stach1-11/+0
The power saving status bit will not signal if the MMDC is under load, which is likely during kernel boot. There is no point in checking this bit and aborting the probe, as there is nothing depending on power saving being enabled, so we can trust the memory controller to enable power saving when we allow it. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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