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2011-03-17Merge branch 'misc' into develRussell King10-23/+65
Conflicts: arch/arm/Kconfig
2011-03-17Merge branches 'at91', 'ep93xx', 'errata', 'footbridge', 'fncpy', 'gemini', ↵Russell King18-641/+851
'irqdata', 'pm', 'sh', 'smp', 'spear', 'ux500' and 'via' into devel
2011-03-15ARM: 6806/1: irq: introduce entry and exit functions for chained handlersWill Deacon1-0/+31
Some chained IRQ handlers are written to cope with primary chips of potentially different flow types. Whether this a sensible thing to do is a point of contention. This patch introduces entry/exit functions for chained handlers which infer the flow type of the primary chip as fasteoi or level-type by checking whether or not the ->irq_eoi function pointer is present and calling back to the primary chip as necessary. Other methods of flow control are not considered. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-10ARM: 6798/1: aout-core: zero thread debug registers in a.out core dumpWill Deacon2-6/+2
The removal of the single-step emulation from ptrace on ARM means that thread_struct no longer has software breakpoint fields in its debug member. This patch fixes the a.out core dump code so that the debug registers are zeroed rather than trying to copy from non-existent fields. Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Bryan Wu <bryan.wu@canonical.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-10ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9Will Deacon1-1/+1
On revisions of the Cortex-A9 prior to r2p0, the Store Buffer does not have any automatic draining mechanism and therefore a livelock may occur if an external agent continuously polls a memory location waiting to observe an update. This workaround defines cpu_relax() as smp_mb(), preventing correctly written polling loops from denying visibility of updates to memory. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-09ARM: 6777/1: gic: Add hooks for architecture specific extensionsSantosh Shilimkar1-0/+1
Few architectures combine the GIC with an external interrupt controller. On such systems it may be necessary to update both the GIC registers and the external controller's registers to control IRQ behavior. This can be addressed in couple of possible methods. 1. Export common GIC routines along with 'struct irq_chip gic_chip' and allow architectures to have custom function by override. 2. Provide architecture specific function pointer hooks within GIC library and leave platforms to add the necessary code as part of these hooks. First one might be non-intrusive but have few shortcomings like arch needs to have there own custom gic library. Locks used should be common since it caters to same IRQs etc. Maintenance point of view also it leads to multiple file fixes. The second probably is cleaner and portable. It ensures that all the common GIC infrastructure is not touched and also provides archs to address their specific issue. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Colin Cross <ccross@android.com> Tested-by: Colin Cross <ccross@android.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-09ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corruptiSantosh Shilimkar1-0/+1
PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. Workaround: Disable Write-Back and Cache Linefill (Debug Control Register) Clean & Invalidate by Way (0x7FC) Re-enable Write-Back and Cache Linefill (Debug Control Register) This patch also removes any OMAP dependency on PL310 Errata's Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-26ARM: 6765/1: remove obsolete comment from asm/mach/arch.hNicolas Pitre1-4/+0
Since commit 6fc31d54 this comment is no longer true. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-23ARM: 6668/1: ptrace: remove single-step emulation codeWill Deacon3-14/+1
PTRACE_SINGLESTEP is a ptrace request designed to offer single-stepping support to userspace when the underlying architecture has hardware support for this operation. On ARM, we set arch_has_single_step() to 1 and attempt to emulate hardware single-stepping by disassembling the current instruction to determine the next pc and placing a software breakpoint on that location. Unfortunately this has the following problems: 1.) Only a subset of ARMv7 instructions are supported 2.) Thumb-2 is unsupported 3.) The code is not SMP safe We could try to fix this code, but it turns out that because of the above issues it is rarely used in practice. GDB, for example, uses PTRACE_POKETEXT and PTRACE_PEEKTEXT to manage breakpoints itself and does not require any kernel assistance. This patch removes the single-step emulation code from ptrace meaning that the PTRACE_SINGLESTEP request will return -EIO on ARM. Portable code must check the return value from a ptrace call and handle the failure gracefully. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-23ARM: 6639/1: allow highmem on SMP platforms without h/w TLB ops broadcastNicolas Pitre1-2/+27
In commit e616c591405c168f6dc3dfd1221e105adfe49b8d, highmem support was deactivated for SMP platforms without hardware TLB ops broadcast because usage of kmap_high_get() requires that IRQs be disabled when kmap_lock is locked which is incompatible with the IPI mechanism used by the software TLB ops broadcast invoked through flush_all_zero_pkmaps(). The reason for kmap_high_get() is to ensure that the currently kmap'd page usage count does not decrease to zero while we're using its existing virtual mapping in an atomic context. With a VIVT cache this is essential to do due to cache coherency issues, but with a VIPT cache this is only an optimization so not to pay the price of establishing a second mapping if an existing one can be used. However, on VIPT platforms without hardware TLB maintenance we can give up on that optimization in order to be able to use highmem. From ARMv7 onwards the TLB ops are broadcasted in hardware, so let's disable ARCH_NEEDS_KMAP_HIGH_GET only when CONFIG_SMP and CONFIG_CPU_TLB_V6 are defined. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Saeed Bishara <saeed.bishara@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-23ARM: fix some sparse errors in generic ARM codeRussell King1-1/+2
arch/arm/kernel/return_address.c:37:6: warning: symbol 'return_address' was not declared. Should it be static? arch/arm/kernel/setup.c:76:14: warning: symbol 'processor_id' was not declared. Should it be static? arch/arm/kernel/traps.c:259:1: warning: symbol 'die_lock' was not declared. Should it be static? arch/arm/vfp/vfpmodule.c:156:6: warning: symbol 'vfp_raise_sigfpe' was not declared. Should it be static? Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-23ARM: 6757/1: fix tlb.h induced linux/swap.h build failureUwe Kleine-König1-0/+2
Commit 06824ba (ARM: tlb: delay page freeing for SMP and ARMv7 CPUs) introduced a build failure for builds with CONFIG_SWAP=n: In file included from arch/arm/mm/init.c:27: arch/arm/include/asm/tlb.h: In function 'tlb_flush_mmu': arch/arm/include/asm/tlb.h:101: error: implicit declaration of function 'release_pages' arch/arm/include/asm/tlb.h: In function 'tlb_remove_page': arch/arm/include/asm/tlb.h:165: error: implicit declaration of function 'page_cache_release' as linux/swap.h doesn't include linux/pagemap.h but actually needs it (see comments in linux/swap.h as to why this is.) Fix that by #including <linux/pagemap.h> in <asm/pgalloc.h> as it's done by x86. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-22ARM: pm: add generic CPU suspend/resume supportRussell King2-0/+10
This adds core support for saving and restoring CPU coprocessor registers for suspend/resume support. This contains support for suspend with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs. Tested on Assabet and Tegra 2. Tested-by: Colin Cross <ccross@android.com> Tested-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-21ARM: tlb: move noMMU tlb_flush() to asm/tlb.hRussell King2-6/+4
There's no need to noMMU to put tlb_flush() in asm/tlbflush.h - it's part of the tlb shootdown interface. Move it to asm/tlb.h instead, as per x86. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-21ARM: tlb: delay page freeing for SMP and ARMv7 CPUsRussell King1-13/+89
We need to delay freeing any mapped page on SMP and ARMv7 systems to ensure that the data is not accessed by other CPUs, or is used for speculative prefetch with ARMv7. This includes not only mapped pages but also pages used for the page tables themselves. This avoids races with the MMU/other CPUs accessing pages after they've been freed but before we've invalidated the TLB. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-21ARM: 6722/1: SPEAr: sp810: switch to slow mode before resetShiraz Hashim1-0/+3
In sysctl_soft_reset(), switch to slow mode before resetting the system via the system controller. This is required. Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-19ARM: 6741/1: errata: pl310 cache sync operation may be faultySrinidhi Kasagar1-0/+1
The effect of cache sync operation is to drain the store buffer and wait for all internal buffers to be empty. In normal conditions, store buffer is able to merge the normal memory writes within its 32-byte data buffers. Due to this erratum present in r3p0, the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. This can severely affect performance on the write traffic esp. on Normal memory NC one. The proposed workaround is to replace the normal offset of cache sync operation(0x730) by another offset targeting an unmapped PL310 register 0x740. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-12ARM: move cache/processor/fault glue to separate include filesRussell King9-617/+640
This allows the cache/processor/fault glue to be more easily used from assembler code. Tested on Assabet and Tegra 2. Tested-by: Colin Cross <ccross@android.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-11ARM: pm: add function to set WFI low-power mode for SMP CPUsRussell King1-0/+7
Add a function to set the SCU low-power mode for SMP CPUs. This centralizes this functionality rather than having to expose the SCU register definitions to each platform. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-31ARM: io: ensure inb/outb() et.al. are properly ordered on ARMv6+Russell King1-16/+17
Ensure that the ISA/PCI IO space accessors are properly ordered on ARMv6+ architectures. These should always be ordered with respect to all other accesses. This also fixes __iormb() and __iowmb() not being visible to ioread/ iowrite if a platform defines its own MMIO accessors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-27ARM: 6640/1: Thumb-2: Symbol manipulation macros for function body copyingDave Martin1-0/+94
In low-level board support code, there is sometimes a need to copy a function body to another location at run-time. A straightforward call to memcpy doesn't work in Thumb-2, because bit 0 of external Thumb function symbols is set to 1, indicating that the function is Thumb. Without corrective measures, this will cause an off-by-one copy, and the copy may be called using the wrong instruction set. This patch adds an fncpy() macro to help with such copies. Particular care is needed, because C doesn't guarantee any defined behaviour when casting a function pointer to any other type. This has been observed to lead to strange optimisation side-effects when doing the arithmetic which is required in order to copy/move function bodies correctly in Thumb-2. Thanks to Russell King and Nicolas Pitre for their input on this patch. Signed-off-by: Dave Martin <dave.martin@linaro.org> Tested-by: Jean Pihet <j-pihet@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-26ARM: 6637/1: Make the argument to virt_to_phys() "const volatile"Catalin Marinas1-1/+1
Changing the virt_to_phys() argument to "const volatile void *" avoids compiler warnings in some situations where this function is used. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-25ARM: 6635/2: Configure reference clock for Versatile Express timersPawel Moll1-0/+6
Timers on Versatile Express mainboard are used as system clock/event sources. Driver assumes that they are clocked with 1MHz signal. Old V2M firmware apparently configured it by default, but on newer boards one can observe that "sleep 1" command takes over 30 seconds to finish, as the timers are fed with 32kHz instead... This patch performs required magic and also removes code clearing timer's control registers, as exactly the same operations are performed by the timer driver few jiffies later. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-15Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2-1/+3
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: fix missing branch in __error_a ARM: fix /proc/$PID/stack on SMP ARM: Fix build regression on SA11x0, PXA, and H720x targets ARM: 6625/1: use memblock memory regions for "System RAM" I/O resources ARM: fix wrongly patched constants ARM: 6624/1: fix dependency for CONFIG_SMP_ON_UP ARM: 6623/1: Thumb-2: Fix out-of-range offset for Thumb-2 in proc-v7.S ARM: 6622/1: fix dma_unmap_sg() documentation ARM: 6621/1: bitops: remove condition code clobber for CLZ ARM: 6620/1: Change misleading warning when CONFIG_CMDLINE_FORCE is used ARM: 6619/1: nommu: avoid mapping vectors page when !CONFIG_MMU ARM: sched_clock: make minsec argument to clocks_calc_mult_shift() zero ARM: sched_clock: allow init_sched_clock() to be called early ARM: integrator: fix compile warning in cpu.c ARM: 6616/1: Fix ep93xx-fb init/exit annotations ARM: twd: fix display of twd frequency ARM: udelay: prevent math rounding resulting in short udelays
2011-01-12ARM: 6621/1: bitops: remove condition code clobber for CLZRabin Vincent1-1/+1
The CLZ instruction does not alter the condition flags, so remove the "cc" clobber from the inline asm for fls(). Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-11ARM: sched_clock: allow init_sched_clock() to be called earlyRussell King1-0/+2
sched_clock is supposed to be initialized early - in the recently added init_early platform hook. However, in doing so we end up calling mod_timer() before the timer lists are initialized, resulting in an oops. Split the initialization in two - the part which the platform calls early which starts things off. The addition of the timer can be delayed until after we have more of the kernel initialized - when the normal time sources are initialized. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-07Merge branch 'omap-for-linus' of ↵Linus Torvalds1-1/+11
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (243 commits) omap2: Make OMAP2PLUS select OMAP_DM_TIMER OMAP4: hwmod data: Fix alignment and end of line in structurefields OMAP4: hwmod data: Move the DMA structures OMAP4: hwmod data: Move the smartreflex structures OMAP4: hwmod data: Fix missing SIDLE_SMART_WKUP in smartreflexsysc arm: omap: tusb6010: add name for MUSB IRQ arm: omap: craneboard: Add USB EHCI support omap2+: Initialize serial port for dynamic remuxing for n8x0 omap2+: Add struct omap_board_data and use it for platform level serial init omap2+: Allow hwmod state changes to mux pads based on the state changes omap2+: Add support for hwmod specific muxing of devices omap2+: Add omap_mux_get_by_name OMAP2: PM: fix compile error when !CONFIG_SUSPEND MAINTAINERS: OMAP: hwmod: update hwmod code, data maintainership OMAP4: Smartreflex framework extensions OMAP4: hwmod: Add inital data for smartreflex modules. OMAP4: PM: Program correct init voltages for scalable VDDs OMAP4: Adding voltage driver support OMAP4: Register voltage PMIC parameters with the voltage layer OMAP3: PM: Program correct init voltages for VDD1 and VDD2 ... Fix up trivial conflict in arch/arm/plat-omap/Kconfig
2011-01-07Merge branch 'devel-stable' into develRussell King1-2/+2
Conflicts: arch/arm/mach-pxa/clock.c arch/arm/mach-pxa/clock.h
2011-01-07Merge branch 'pgt' (early part) into develRussell King3-190/+181
2011-01-07Merge branch 'misc' into develRussell King18-105/+239
Conflicts: arch/arm/Kconfig arch/arm/common/Makefile arch/arm/kernel/Makefile arch/arm/kernel/smp.c
2011-01-07Merge branch 'smp' into miscRussell King11-45/+57
Conflicts: arch/arm/kernel/entry-armv.S arch/arm/mm/ioremap.c
2011-01-07ARM: DMA: add support for DMA debuggingRussell King1-12/+53
Add ARM support for the DMA debug infrastructure, which allows the DMA API usage to be debugged. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-05Merge branch 'clksrc' into develRussell King3-2/+144
Conflicts: arch/arm/mach-vexpress/v2m.c arch/arm/plat-omap/counter_32k.c arch/arm/plat-versatile/Makefile
2011-01-05Merge branches 'ftrace', 'gic', 'io', 'kexec', 'mod', 'sa11x0', 'sh' and ↵Russell King7-24/+108
'versatile' into devel
2011-01-04Merge branch 'fix' of ↵Russell King1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
2011-01-03ARM: it8152: add IT8152_LAST_IRQ definition to fix build errorMike Rapoport1-0/+1
The commit 6ac6b817f3f4c23c5febd960d8deb343e13af5f3 (ARM: pxa: encode IRQ number into .nr_irqs) removed definition of ITE_LAST_IRQ which caused the following build error: CC arch/arm/common/it8152.o arch/arm/common/it8152.c: In function 'it8152_init_irq': arch/arm/common/it8152.c:86: error: 'IT8152_LAST_IRQ' undeclared (first use in this function) arch/arm/common/it8152.c:86: error: (Each undeclared identifier is reported only once arch/arm/common/it8152.c:86: error: for each function it appears in.) make[2]: *** [arch/arm/common/it8152.o] Error 1 Defining the IT8152_LAST_IRQ in the arch/arm/include/hardware/it8152.c fixes the build. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2011-01-03ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()Russell King1-15/+19
Replace the page_to_dma() and dma_to_page() macros with their PFN equivalents. This allows us to map parts of memory which do not have a struct page allocated to them to bus addresses. This will be used internally by dma_alloc_coherent()/dma_alloc_writecombine(). Build tested on Versatile, OMAP1, IOP13xx and KS8695. Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-03ARM: 6605/1: Add missing include "asm/memory.h"Axel Lin1-0/+1
This patch fixes below build error by adding the missing asm/memory.h, which is needed for arch_is_coherent(). $ make pxa3xx_defconfig; make CC init/do_mounts_rd.o In file included from include/linux/list_bl.h:5, from include/linux/rculist_bl.h:7, from include/linux/dcache.h:7, from include/linux/fs.h:381, from init/do_mounts_rd.c:3: include/linux/bit_spinlock.h: In function 'bit_spin_unlock': include/linux/bit_spinlock.h:61: error: implicit declaration of function 'arch_is_coherent' make[1]: *** [init/do_mounts_rd.o] Error 1 make: *** [init] Error 2 Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Peter Huewe <peterhuewe@gmx.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-24ARM: 6541/1: move sev definition to common system.h include fileShiraz Hashim1-0/+7
sev is used to send wakeup event to other cores in ARMv6K and above. This has been moved from platform specific part to standard common ARM header file (asm/system.h). Also introduced wfi() and wfe(). Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-24ARM: provide an early platform initialization hookRussell King1-0/+1
This allows platforms to hook into the initialization early to setup things like scheduler clocks, etc. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-24ARM: simplify early machine init hooksRussell King3-3/+5
Rather than storing each machine init hook separately, store a pointer to the machine description record and dereference this instead. This pointer is only available while the init sections are present, which is not a problem as we only use it from init code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-24ARM: 6538/1: Subarch IRQ handler macros V3Magnus Damm1-0/+44
Per subarch interrupt handler macros V3. This patch breaks out code from the irq_handler macro into arch_irq_handler and arch_irq_handler_default. The macros are put in the header file "entry-macro-multi.S" The arch_irq_handler_default macro is designed to be used by irq_handler in entry-armv.S while arch_irq_handler is suitable for per-subarch use. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-24ARM: 6532/1: Allow machine to specify it's own IRQ handlers at run-timeeric miao2-0/+7
Normally different ARM platform has different way to decode the IRQ hardware status and demultiplex to the corresponding IRQ handler. This is highly optimized by macro irq_handler in entry-armv.S, and each machine defines their own macro to decode the IRQ number. However, this prevents multiple machine classes to be built into a single kernel. By allowing each machine to specify thier own handler, and making function pointer 'handle_arch_irq' to point to it at run time, this can be solved. And introduce CONFIG_MULTI_IRQ_HANDLER to allow both solutions to work. Comparing with the highly optimized macro of irq_handler, the new function must be written with care not to lose too much performance. And the IPI stuff on SMP is expected to move to the provided arch IRQ handler as well. The assembly code to invoke handle_arch_irq is optimized by Russell King. Signed-off-by: Eric Miao <eric.miao@canonical.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-24ARM: 6536/1: Add missing SZ_{32,64,128}Stephen Warren1-3/+3
... and also remove misleading comment stating that this header is auto-generated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Uwe Kleine-Knig <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-23ARM: sched_clock: provide common infrastructure for sched_clock()Russell King1-0/+118
Provide common sched_clock() infrastructure for platforms to use to create a 64-bit ns based sched_clock() implementation from a counter running at a non-variable clock rate. This implementation is based upon maintaining an epoch for the counter and an epoch for the nanosecond time. When we desire a sched_clock() time, we calculate the number of counter ticks since the last epoch update, convert this to nanoseconds and add to the epoch nanoseconds. We regularly refresh these epochs within the counter wrap interval. We perform a similar calculation as above, and store the new epochs. We read and write the epochs in such a way that sched_clock() can easily (and locklessly) detect when an update is in progress, and repeat the loading of these constants when they're known not to be stable. The one caveat is that sched_clock() is not called in the middle of an update. We achieve that by disabling IRQs. Finally, if the clock rate is known at compile time, the counter to ns conversion factors can be specified, allowing sched_clock() to be tightly optimized. We ensure that these factors are correct by providing an initialization function which performs a run-time check. Acked-by: Peter Zijlstra <peterz@infradead.org> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Mikael Pettersson <mikpe@it.uu.se> Tested-by: Eric Miao <eric.y.miao@gmail.com> Tested-by: Olof Johansson <olof@lixom.net> Tested-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-22ARM: pgtable: provide RDONLY page table bit rather than WRITE bitRussell King1-19/+19
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-22ARM: pgtable: invert L_PTE_EXEC to L_PTE_XNRussell King1-22/+22
The hardware page tables use an XN bit 'execute never'. Historically, we've had a Linux 'execute allow' bit, in the positive sense. Get rid of this artifact as future hardware will continue to have the XN sense. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-22ARM: pgtable: remove FIRST_USER_PGD_NRRussell King1-2/+1
FIRST_USER_PGD_NR is now unnecessary, as this has been replaced by FIRST_USER_ADDRESS except in the architecture code. Fix up the last usage of FIRST_USER_PGD_NR, and remove the definition. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-22ARM: pgtable: collect up identity mapping functionsRussell King1-0/+3
We have two places where we create identity mappings - one when we bring secondary CPUs online, and one where we setup some mappings for soft- reboot. Combine these two into a single implementation. Also collect the identity mapping deletion function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-22ARM: pgtable: switch order of Linux vs hardware page tablesRussell King2-38/+32
This switches the ordering of the Linux vs hardware page tables in each page, thereby eliminating some of the arithmetic in the page table walks. As we now place the Linux page table at the beginning of the page, we can deal with the offset in the pgt by simply masking it away, along with the other control bits. This also makes the arithmetic all be positive, rather than a mixture. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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