| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
LG Optimus Vu (p895) and Optimus 4X HD (p880) have 266.5MHz RAM
clock and require this entry to work with it correctly.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Accelerometer mount matrix used in tf101 downstream is inverted.
This new matrix was generated on actual device using calibration
script, like on other transformers.
Tested-by: Robert Eckelmann <longnoserob@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Add aliases for eMMC, SD card and WiFi where applicable, so that
assigned mmc indeces are always the same.
Co-developed-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
[ Tested on exynos5800-peach-pi ]
Tested-by: Valentine Iourine <iourine@iourine.msk.su>
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20230402144724.17839-3-henrik@grimler.se
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
Previously, the mshc0 alias has been necessary so that
MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA are set for mshc_0/mmc_0.
However, these capabilities should be described in the device tree so
that we do not have to rely on the alias.
The property mmc-ddr-1_8v replaces MMC_CAP_1_8V_DDR, while bus_width =
<8>, which is already set for all the mshc0/mmc0 nodes, replaces
MMC_CAP_8_BIT_DATA.
Also drop other mshc aliases as they are not needed.
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20230402144724.17839-2-henrik@grimler.se
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
Add QSPI support on STM32MP13x SoC family
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
Add FMC support on STM32MP13x SoC family.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
"make dtbs_check" gives following output :
stm32mp157c-emstamp-argon.dtb: gpu@59000000: 'contiguous-area' does not match
any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
"make dtbs_check" gives following output :
stm32mp157c-odyssey.dt.yaml: gpu@59000000: 'contiguous-area' does not match
any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
"make dtbs_check" gives following output :
stm32mp157x-xxx.dt.yaml: gpu@59000000: 'contiguous-area' does not match
any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml
Solve this trouble for STM32MPU Boards :
- stm32mp157c-ed1
- stm32mp157x-dkx
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
frequency
sam9x60ek populates an sst26vf064b SPI NOR flash. Its maximum operating
frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
increase its maximum supported frequency to 104MHz. The increasing of the
spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~33%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20230328101517.1595738-5-tudor.ambarus@linaro.org
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
|
|
frequency
sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating
frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
increase its maximum supported frequency to 104MHz. The increasing of the
spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~37%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Tested-by: Nicolas Ferre <nicolas.ferre@microchip.com> # on sama5d2 ICP
Link: https://lore.kernel.org/r/20230328101517.1595738-4-tudor.ambarus@linaro.org
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
|
|
frequency
sama5d27-som1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~37%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20230328101517.1595738-3-tudor.ambarus@linaro.org
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
|
|
frequency
sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~37%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20230328101517.1595738-2-tudor.ambarus@linaro.org
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
|
|
Add support for the 7 PWM channels provided by PWM Timers on R-Car H2,
by adding device nodes describing the PWM Timers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/9755b3af4296060ee31c4652def639574cbbd2fb.1679330878.git.geert+renesas@glider.be
|
|
Add support for the 4 PWM channels provided by the 16-bit Timer Pulse
Unit on R-Car H2, by adding a device node describing the TPU.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/75da1e63135a3fc8a3aaafbff7139bd5d7509be3.1679330727.git.geert+renesas@glider.be
|
|
Enable the single I2C bus available on the Marzen development board.
As this bus contains an AK4643 codec, it must be limited to 100 kHz.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/77b87378397fd26f39c73f68e3ea465db6d38fb1.1679330016.git.geert+renesas@glider.be
|
|
Describe the four General Purpose Switches on the Marzen development
board, so they can be used for user input and/or for wake-up from s2ram.
The GPIO block on R-Car H1 does not support triggering interrupts on
both edges of a changing input signal, hence one cannot use gpio-keys
with gpios properties. Instead, one of two alternatives needs to be
used:
1. Use gpio-keys with interrupts instead of gpios properties, at the
expense of receiving only key presses (release events will be
auto-generated),
2. Use gpio-keys-polled with gpios properties, at the expense of
making these keys unusable as wake-up sources.
As the DTS for the Marzen development board serves mainly as an example,
the approach taken is to use the first alternative for the first two
switches, and the second alternative for the last two switches.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f834a3c397362f2424fcae6a0c0440356208b182.1679329829.git.geert+renesas@glider.be
|
|
Add support for the 7 PWM channels provided by PWM Timers on R-Car
H1, by describing the PWM Timers and their module clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/71622584db692f571d542ef2dcf088ce549aed3f.1679329211.git.geert+renesas@glider.be
|
|
Per binding doc, update the compatible
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20230322052504.2629429-11-peng.fan@oss.nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
Update device-tree stm32mp135f-dk.dts to add usart1, uart8, usart2
and uart aliases.
- Usart2 is used to interface a BT device, enable it by default.
- Usart1 and uart8 are available on expansion connector.
They are kept disabled. So, the pins are kept in analog state to
lower power consumption by default or can be used as GPIO.
- Uart4 is used for console.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
Add pins for uart4, uart8, usart1 and usart2 in stm32mp13-pinctrl.dtsi
Theses pins have three states: default, sleep and idle.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
Update device-tree stm32mp131.dtsi to add some uart features.
On uart 1, 2, 3, 5, 6, 7, 8 nodes, add compabible, exti interrupts, clock,
reset properties, dma config.
On uart 4 node, only add dma configuration and use exti interrupt.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
Remove duplicates and clean uart aliases.
Uart aliases and uart pins should be declared and associated to
uart instance at the same time.
Put also aliases node above chosen node as same as stm32mp157c-dk2.dts.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
Remove duplicates and clean uart aliases.
Uart aliases and uart pins should be declared and associated to
uart instance at the same time.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
On stm32mp15xx-dkx boards:
- Fix slew-rate of USART 2 to 0 like other USARTs, because frequency of
USART pins doesn't exceed 10Mhz.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
TF201, TF300TG and TF700T support RT5631 codec.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Fix headset detection and use device GPIO microphone detection on WM8903
Transformers.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Add pin configurations for using CAN controller on stm32f469-disco
board. They are located on the Arduino compatible connector CN5 (CAN1)
and on the extension connector CN12 (CAN2).
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230328073328.3949796-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
|
|
Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The
chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary,
that share some of the required logic like clock and filters. This means
that the secondary CAN can't be used without the primary CAN.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230328073328.3949796-4-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
|
|
Bank A and B IOs can't be handled by the pin controller 'Z'. This patch
assign spi1 pin definition to the correct controller.
Fixes: 9ad65d245b7b ("ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group")
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
"simple-panel" compatible is not documented and nothing in Linux kernel
binds to it.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
This was not matched anywhere and provides no additional information. The
driver code already checks also for "ti,omap3630" compatible.
Signed-off-by: Andrew Davis <afd@ti.com>
Message-Id: <20230216153339.19987-2-afd@ti.com>
[tony@atomide.com: updated comments for ti,omap3630 compatible]
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
The MangoPi MQ-R-T113 is a small SBC with the Allwinner T113-s3 SoC.
The SoC features two Arm Cortex-A7 cores and 128 MB of co-packaged DDR3
DRAM. The board adds mostly connectors and the required regulators, plus
a Realtek RTL8189FTV WiFi chip.
Power comes in via a USB-C connector wired as a peripheral, and there is
a second USB-C connector usable as a host port.
Add a .dtsi file describing most of the board's peripherals, and include
that from the actual board .dts file. This allows to re-use the .dtsi
for the MQ-R-F113 RISC-V variant of that board.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230320005249.13403-5-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
|
The Allwinner T113-s SoC is apparently using the same (or at least a very
similar) die as the D1/D1s, but replaces the single RISC-V core with
two Arm Cortex-A7 cores.
Since the D1 core .dtsi already describes all common peripherals, we
just need a DT describing the ARM specific peripherals: the CPU cores,
the Generic Timer, the GIC and the PMU.
We include the core .dtsi directly from the riscv DT directory.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230320005249.13403-3-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
|
According to docu and dtschema check, 'gpmc,device-nand = true' is
no longer valid, so remove it.
Signed-off-by: Steffen Hemer <s.hemer@phytec.de>
Message-Id: <20230214132302.39087-8-s.hemer@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
According to docu and dtschema check, 'linux,default-trigger = gpio' is
no longer valid, so remove it.
Signed-off-by: Steffen Hemer <s.hemer@phytec.de>
Message-Id: <20230214132302.39087-7-s.hemer@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Remove underscore in node names following conventions.
Signed-off-by: Steffen Hemer <s.hemer@phytec.de>
Message-Id: <20230214132302.39087-6-s.hemer@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Remove underscore in node names following conventions.
Signed-off-by: Steffen Hemer <s.hemer@phytec.de>
Message-Id: <20230214132302.39087-5-s.hemer@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Remove underscore in node names following conventions.
Signed-off-by: Steffen Hemer <s.hemer@phytec.de>
Message-Id: <20230214132302.39087-4-s.hemer@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Change node name of sound card to recommended generic and remove also
further underscores in other node names.
Signed-off-by: Steffen Hemer <s.hemer@phytec.de>
Message-Id: <20230214132302.39087-3-s.hemer@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Sound did not work with the previous EVM sound card binding, EVM dts
switched to using 'simple-audio-card', so this fixes audio codec by using
simple-audio-card driver.
Signed-off-by: Steffen Hemer <s.hemer@phytec.de>
Message-Id: <20230214132302.39087-2-s.hemer@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Without an alias for the TPS65910 RTC, it snatches the rtc0 device in
advance to the I2C RTC assigned to that alias.
Signed-off-by: Steffen Hemer <s.hemer@phytec.de>
Message-Id: <20230214132302.39087-1-s.hemer@phytec.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Vendor of the GTA04 boards is and always was
Golden Delicious Computers GmbH&Co. KG, Germany
and not Texas Instruments.
Maybe, TI was references here because the GTA04 was based on
the BeagleBoard design which is designated as "ti,omap3-beagle".
While we are looking at vendors of omap3 based devices, we also
add the record for OpenPandora. The DTS files for the pandora
device already make use of it.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Message-Id: <38b49aad0cf33bb5d6a511edb458139b58e367fd.1676566002.git.hns@goldelico.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
OMAP processors support 32 channels but there is no check or
inspect this except booting a device and looking at dmesg reports
of not available channels.
Recently some more subsystems with DMA (aes1+2) were added filling
the list of dma channels beyond the limit of 32 (even if other
parameters indicate 96 or 128 channels). This leads to random
subsystem failures i(e.g. mcbsp for audio) after boot or boot
messages that DMA can not be initialized.
Another symptom is that
/sys/kernel/debug/dmaengine/summary
has 32 entries and does not show all required channels.
Fix by disabling unused (on the GTA04 hardware) mcspi1...4.
Each SPI channel allocates 4 DMA channels rapidly filling
the available ones.
Disabling unused SPI modules on the OMAP3 SoC may also save
some energy (has not been checked).
Fixes: c312f066314e ("ARM: dts: omap3: Migrate AES from hwmods to sysc-omap2")
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
[re-enabled aes2, improved commit subject line]
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Message-Id: <20230113211151.2314874-1-andreas@kemnade.info>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
This is a more interesting use of DT Overlays than the previous patches.
Here we have two touchscreen modules. Each is compatible with, and can be
attached to, either of the two AM57xx IDK development board variants
(AM571x or AM572x).
Due to the way the extension header was wired on the development boards,
the touch sensor on the touchscreen modules will connect to different
SoC pins when connected. For this the touch sensor is modeled as an
additional overlay that is specific to the development board for which it
is connected.
Basically the LCD overlay can be swapped, but the touchscreen overlay
that attaches to the LCD must be used with the corresponding base DT
and not to the LCD.
AM571x -\ /- osd101t2045.dtbo -\ /- am571x-idk-touchscreen.dtbo
X X
AM572x -/ \- osd101t2587.dtbo -/ \- am572x-idk-touchscreen.dtbo
Signed-off-by: Andrew Davis <afd@ti.com>
Message-Id: <20230307161715.15209-4-afd@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
The A3 revision of the AM57xx GP EVM has the same EVM feature set as the
original but is paired with an updated revision C BeagleBoard X15.
DT Overlays allow us to model this in the same way, we simply apply the
EVM overlay to the Rev C BeagleBoard to create the Rev A3 AM57xx GP EVM.
Signed-off-by: Andrew Davis <afd@ti.com>
Message-Id: <20230307161715.15209-3-afd@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
The AM57xx GP EVM boards are built on top the AM57xx BeagleBoard-X15.
The EVM extends the BeagleBoard by adding a touchscreen, some buttons,
and a handful of peripheral extension slots.
Being a plugin extension of an existing standalone board; we define
the am57xx-evm as a composite-DTB of the base am57xx-beagle-x15
and a new am57xx-evm overlay.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Message-Id: <20230307161715.15209-2-afd@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Add a devicetree for the Tolino Vision Ebook reader. It is based
on boards marked with "37NB-E60Q30+4A3". It is equipped with an i.MX6SL
SoC.
Expected to work:
- Buttons
- Wifi
- LEDs
- uSD
- eMMC
- USB
- RTC
- Touchscreen
- Backlight
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
The PCB used for all the current boards (Ursa, Draco, Hydra, Orion, Crux)
was slightly redesigned and delivers some new features while some unused
components were removed.
- External RTC chip with supercap added.
- Secure element added.
- LCD display power supply enable/disable signal added.
- Touch keyboard reset and interrupt signals added.
- Factory reset GPIO button added.
- Audio codec LM49350 (EoL) removed and replaced by PWM audio output.
- QCA8334 switch was replaced by Marvell 88E6141.
- PCIe completely removed.
- uSD card removed and replaced by board-to-board expansion connector.
There are four configuration variants of the new board:
1. Pegasus
The board configuration is based on Orion with the following major changes:
- Quad core SoC
- 4GB of RAM
- RTC with supercap added
- Secure element added
2. Pegasus+
This is the very same board as Pegasus but uses the i.MX6QuadPlus SoC.
3. Lynx
The board configuration is based on Draco with the following major changes:
- DualLite SoC
- 1GB of RAM
- RTC with supercap added
- Secure element added
4. Phoenix
The board configuration is based on Ursa with the following major changes:
- DualLite Soc
- 1GB of RAM
- RTC with supercap added
- Secure element added
- LCD display support removed
- UART2 removed
- Factory reset GPIO button added
Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Explicit status = "okay" is not needed as it is the default.
Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
