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2018-11-28ARM: dts: sun6i: Change clock node names to avoid warningsMaxime Ripard1-4/+4
Our oscillators clock names have a unit address, but no reg property, which generates a warning in DTC. Change these names to remove those unit addresses. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun6i: Change framebuffer node names to avoid warningsMaxime Ripard1-2/+2
The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun6i: Remove skeleton and memory to avoid warningsMaxime Ripard1-6/+2
Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Provide default muxing for relevant controllersMaxime Ripard16-94/+13
The I2C's, MMC0 and MMC1 controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: A10s: Remove empty SRAM nodeMaxime Ripard1-3/+0
The SRAM node in the A10s DTSI is empty, remove it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sunxi: Change LRADC node names to avoid warningsMaxime Ripard1-2/+2
One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Remove underscores from nodes namesMaxime Ripard11-21/+20
Some GPIO pinctrl nodes cannot be easily removed, because they would also change the pin configuration, for example to add a pull resistor or change the current delivered by the pin. Those nodes still have underscores and unit-addresses in their node names in our DTs, so adjust their name to remove the warnings. Use that occasion to also fix some poorly chosen node-names. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sunxi: Remove the CMA node labelMaxime Ripard4-4/+4
There's no phandle pointing to the CMA pool, so it's label is unnecessary. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sunxi: Change default CMA pool node nameMaxime Ripard4-4/+4
The CMA node has a unit address, but no reg property which generates a warning in DTC. Change the node name to reflect its usage and drop the unit address. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: r9a06g032: Correct the GIC DT node namePhil Edworthy1-1/+1
Harmless mistake, but it's incorrect. The DT spec provides recommendations for the node names: "The name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model. If appropriate, the name should be one of the following choices: ... interrupt-controller" Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: iwg23s-sbc: Add QSPI flash supportFabrizio Castro1-0/+26
This commit adds QSPI flash support to the iwg23s board specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add QSPI supportFabrizio Castro1-0/+32
Add QSPI[01] support to the RZ/G1C SoC specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVBBiju Das1-0/+8
Adding pinctrl support for EtherAVB interface. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: iwg23s-sbc: Enable cmt0Biju Das1-0/+4
This patch enables cmt0 support on the iWave iwg23s sbc. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add CMT SoC specific supportBiju Das1-0/+32
Add CMT[01] support to r8a77470 SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add USB-DMAC device nodesBiju Das1-0/+56
This patch adds USB DMAC nodes. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: iwg23s-sbc: Enable watchdog supportBiju Das1-0/+5
This patch enables watchdog support on the iWave iwg23s sbc. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add watchdog support to SoC dtsiBiju Das1-0/+10
This patch adds watchdog support to the r8a77470 SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> [simon: moved node to preserve sort order] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a7740, emev2, sh73a0: Include SoC name in DTSIMagnus Damm3-3/+3
Update the R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and SH-Mobile AG5 (sh72a0) DTSI to include product name. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> [simon: squashed similar patches] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a779[01]: Disable unconnected LVDS encodersLaurent Pinchart3-6/+0
The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager, are enabled in DT but have no device connected to their output. This result in spurious messages being printed to the kernel log such as rcar-du feb00000.display: no connector for encoder /soc/lvds@feb90000, skipping Fix it by disabling the encoders. Fixes: 15a1ff30d8f9 ("ARM: dts: r8a7790: Convert to new LVDS DT bindings") Fixes: e5c3f4707f39 ("ARM: dts: r8a7791: Convert to new LVDS DT bindings") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: iwg23s-sbc: Add uSD and eMMC supportFabrizio Castro1-0/+76
Add uSD card and eMMC support to the iwg23s single board computer powered by the RZ/G1C SoC (a.k.a. r8a77470). Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add SDHI1 supportFabrizio Castro1-0/+11
Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a. r8a77470) is compatible with the R-Car Gen3 ones, its OF compatibility is restricted to the SoC specific compatible string to avoid confusion, as from a more generic perspective the RZ/G1C is sharing the most similarities with the R-Car Gen2 family of SoCs, and there is a combination of R-Car Gen2 compatible SDHI IPs and R-Car Gen3 compatible SDHI IP on this specific chip. This patch adds the SoC specific part of SDHI1 support, and since SDHI1 comes with internal DMA, its DT node looks fairly different from SDHI0 and SDHI2. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add SDHI0 supportFabrizio Castro1-1/+16
RZ/G1C comes with two different types of IP for the SDHI interfaces, SDHI0 and SDHI2 share the same IP type, and such an IP is also compatible with the one found in R-Car Gen2. SDHI1 IP on the other hand is compatible with R-Car Gen3 with internal DMA. This patch completes the SDHI support of the R-Car Gen2 compatible IPs, including fixing the max-frequency definition of SDHI2, as it turns out there is a bug in Section 1.3.9 of the RZ/G1C Hardware User's Manual (Rev. 1.00 Oct. 2017). Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r8a77470: Add I2C[0123] supportFabrizio Castro1-0/+64
Add device tree nodes for the I2C[0123] controllers. Also, add the aliases node. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r9a06g032: Add pinctrl nodePhil Edworthy1-0/+8
This provides a pinctrl driver for the Renesas R9A06G032 SoC Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: sun5i: a10s: Fix HDMI output DTC warningMaxime Ripard1-2/+0
Our HDMI output endpoint on the A10s DTSI has a warning under DTC: "graph node has single child node 'endpoint', #address-cells/#size-cells are not necessary". Fix this by removing those properties. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Change pinctrl nodes to avoid warningMaxime Ripard19-119/+127
All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Remove card detect pull-upMaxime Ripard11-88/+12
Boards usually have an external pull-up on the card-detect signal, so there's no need to add another one. This also removes a DTC warning. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Remove all useless pinctrl nodesMaxime Ripard13-160/+2
The gpio pinctrl nodes are redundant and as such useless most of the times. Since they will also generate warnings in DTC, we can simply remove most of them. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Change LRADC node names to avoid warningsMaxime Ripard6-22/+22
One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Remove redundant interrupt-controllerMaxime Ripard2-4/+0
The interrupt-parent property is set in sun5i.dtsi, so there's no need to repeat it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Remove SoC node unit-name to avoid warningsMaxime Ripard4-4/+4
Our main node for all the in-SoC controllers used to have a unit name. The unit-name, in addition to being actually false, would not match any reg property, which generates a warning. Remove it in order to remove those warnings. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Remove skeleton to avoid warningsMaxime Ripard3-6/+2
Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Change clock node names to avoid warningsMaxime Ripard1-2/+2
Our oscillators clock names have a unit address, but no reg property, which generates a warning in DTC. Change these names to remove those unit addresses. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun5i: Change framebuffer node names to avoid warningsMaxime Ripard2-3/+3
The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun4i: Fix HDMI output DTC warningMaxime Ripard1-2/+0
Our HDMI output endpoint on the A10 DTSI has a warning under DTC: "graph node has single child node 'endpoint', #address-cells/#size-cells are not necessary". Fix this by removing those properties. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28ARM: dts: sun4i: Fix gpio-keys warningMaxime Ripard2-4/+0
Fix the 'unnecessary #address-cells/#size-cells without "ranges" or child "reg" property' DTC warning for the gpio-keys DT node on A10 boards. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-28Merge tag 'tags/bcm2835-dt-next-2018-11-27' into devicetree/nextFlorian Fainelli8-20/+14
This pull request adds a compatible string to the DT necessary for the firmware and VCHI driver to coordinate on using the correct cache line size for the platform. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-11-27ARM: dts: sun8i: Add the H3/H5 CSI controllerMylène Josserand1-0/+22
The H3 and H5 features the same CSI controller that was initially found on the A31. Add a DT node for it. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-27ARM: dts: rockchip: update cpu supplies on rk3188Heiko Stuebner2-2/+26
cpu0-supply in cpu0 is deprecated, instead each cpu-core is supposed to list its supply separately. With the added cpu core phandles, update existing rk3188 boards accordingly. Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
2018-11-27ARM: dts: rockchip: add phandles to secondary cpu coresHeiko Stuebner1-3/+3
Add phandles to secondary cpu cores as we may need to reference these down the road as well. Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
2018-11-27ARM: dts: rockchip: add cpu-core resets for rk3188Heiko Stuebner1-0/+4
Specify the reset handles for each cpu core. Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
2018-11-27ARM: dts: rockchip: convert rk3188 to opp-v2Heiko Stuebner1-11/+44
The fact that OPPs specified only on cpu0 work is Linux specific and normally cpu frequencies should be specified for each cpu core. To facilitate this without needing to duplicate the frequency table each time, convert to opp-v2 before adding references to all cores. Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
2018-11-27ARM: dts: rockchip: add #sound-dai-cells to Cortex-A9 i2sHeiko Stuebner2-0/+4
The Rockchip i2s always just requires a sound-dail-cells value of 0, so add them to the core soc dtsi for convenience. Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
2018-11-27ARM: dts: sun7i: set proper lradc vref on OLinuXino Lime2Olliver Schinagl1-0/+4
The lradc's analog reference voltage is set to 3.0 volt in the hardware. This is more or less set in copper for at least lradc0. Set the property in the dts to ensure the lradc is referenced properly. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-27ARM: dts: rockchip: Add UART DMA support for rv1108Otavio Salvador1-0/+6
Pass the 'dmas' property to the UART ports so that DMA can be supported. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Fabio Berton <fabio.berton@ossystems.com.br> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-27ARM: dts: rockchip: Assign the proper GPIO clocks for rv1108Otavio Salvador1-4/+4
It is not correct to assign the 24MHz clock oscillator to the GPIO ports. Fix it by assigning the proper GPIO clocks instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Fabio Berton <fabio.berton@ossystems.com.br> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-27ARM: dts: rockchip: Fix the PMU interrupt number for rv1108Otavio Salvador1-1/+1
According to the Rockchip vendor tree the PMU interrupt number is 76, so fix it accordingly. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Fabio Berton <fabio.berton@ossystems.com.br> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-26ARM: dts: uniphier: Add all CPUs in cooling mapsViresh Kumar1-2/+4
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-26ARM: dts: rockchip: Pass the 'arm,cpu-registers-not-fw-configured' property ↵Otavio Salvador1-0/+1
on rv1108 Since firmware does not initialize any of the generic timer CPU registers pass the 'arm,cpu-registers-not-fw-configured' property as suggested in Documentation/devicetree/bindings/timer/arm,arch_timer.txt. This also aligns with other Rockchip SoC dtsi files. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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