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2018-12-05ARM: dts: sun8i: h3: Fix the system-control register rangePaul Kocialkowski1-1/+1
Unlike in previous generations, the system-control register range is not limited to a size of 0x30 on the H3. In particular, the EMAC clock configuration register (accessed through syscon) is at offset 0x30 in that range. Extend the register size to its full range (0x1000) as a result. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05ARM: dts: imx7d-pico: Describe the Wifi clockFabio Estevam1-1/+21
The Wifi chip should be clocked by a 32kHz clock coming from i.MX7D CLKO2 output pin, so describe the pinmux and clock hierarchy in the device tree to allow the Wifi chip to be properly clocked. Managed to successfully test Wifi with such change. Used the standard nvram.txt file provided by TechNexion, which selects an external 32kHz clock for the Wifi chip by default. Fixes: 99a52450c707 ("ARM: dts: imx7d-pico: Add Wifi support") Suggested-by: Arend van Spriel <arend.vanspriel@broadcom.com> Tested-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-05ARM: dts: meson: meson8b: add the CPU OPP tablesMartin Blumenstingl1-0/+66
The values are taken from Amlogic's 3.10 kernel sources. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-05ARM: dts: meson: meson8: add the CPU OPP tableMartin Blumenstingl1-0/+72
The values are taken from Amlogic's 3.10 kernel sources. Their sources have a "meson8m2_n200_2G.dtd" which defines a different voltage table: - 0.86V for 96MHz - (values in between omitted) - 1.14V for 1.992GHz The reason for this is simply the hardware design because the voltage regulator on this board is has a minimum output of 0.86V and a maximum output of 1.14V. The recommended settings are added with this patch instead of using the values that are only valid for one board. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-05ARM: dts: meson8b: add the Cortex-A5 global timerMartin Blumenstingl1-0/+13
The Meson8b SoC is using four Cortex-A5 cores. These come with an ARM global timer. This adds the Cortex-A5 global timer but keeps it disabled for now. The timer is clocked by the "PERIPH" clock whose rate can change during runtime (when changing the frequency of the CPU clock). Unfortunately the arm_global_timer driver does not handle changes to the clock rate yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-05ARM: dts: meson8b: add the ARM TWD timerMartin Blumenstingl1-0/+7
The Meson8B SoC is using four ARM Cortex-A5 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on this SoC. Suggested-by: Carlo Caione <carlo@endlessm.com> [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, added the correct clock, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-05ARM: dts: meson8: add the Cortex-A9 global timerMartin Blumenstingl1-0/+13
The Meson8 and Meson8m2 SoCs are using four Cortex-A9 cores. These come with an ARM global timer. This adds the Cortex-A9 global timer but keeps it disabled for now. The timer is clocked by the "PERIPH" clock whose rate can change during runtime (when changing the frequency of the CPU clock). Unfortunately the arm_global_timer driver does not handle changes to the clock rate yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-05ARM: dts: meson8: add the ARM TWD timerMartin Blumenstingl1-0/+7
The Meson8 and Meson8m2 SoC are using four ARM Cortex-A9 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on these two SoCs. Suggested-by: Carlo Caione <carlo@endlessm.com> [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, added the correct clock, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-05ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripheralsMartin Blumenstingl3-18/+30
The public Meson8b (S805) datasheet describes a memory region called "A9 Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a simple-bus node and move all peripherals that are part of this memory region. This makes the .dts a bit easier to read. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: r8a7744: Add PCIe Controller device nodeBiju Das1-0/+28
Add a device node for the PCIe controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add xhci supportBiju Das1-0/+20
Add a device node for the xhci controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add MSIOF[012] supportBiju Das1-0/+48
Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add QSPI supportBiju Das1-0/+16
Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DBBiju Das2-0/+18
This patch adds support for the camera daughter board which is connected to iWave's RZ/G1N Qseven carrier board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add TPU supportBiju Das1-0/+10
Add TPU support to SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add PWM SoC supportBiju Das1-0/+70
Add the definitions for pwm[0123456] to the SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add IPMMU DT nodesBiju Das1-0/+58
Add the six IPMMU instances found in the r8a7744 to DT with a disabled status. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add VSP supportBiju Das1-0/+27
Add VSP support to SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: add VIN dt supportBiju Das1-0/+33
Add VIN[012] support to SoC dt. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add CMT SoC specific supportBiju Das1-0/+32
Add CMT[01] support to SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add thermal device to DTBiju Das1-0/+31
This patch instantiates the thermal sensor module with thermal-zone support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add IRQC supportBiju Das1-0/+20
Describe the IRQC interrupt controller in the r8a7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add CAN supportBiju Das1-2/+20
Add the definitions for can0 and can1 to the r8a7744 SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add audio supportBiju Das1-8/+235
Add sound support for the RZ/G1N SoC (a.k.a. R8A7744). This work is based on similar work done on the R8A7743 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add RWDT nodeBiju Das1-0/+10
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodesBiju Das1-1/+41
Add usb dmac and hsusb device nodes on RZ/G1N SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: USB 2.0 host supportBiju Das1-5/+72
Describe internal PCI bridge devices, USB phy device and link PCI USB devices to USB phy. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20m: Enable SDHI0 controllerBiju Das1-0/+16
Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20m: Add eMMC supportBiju Das1-0/+17
Add eMMC support for iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add MMC nodeBiju Das1-0/+16
Add MMC node to the DT of the r8a7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SDHI nodesBiju Das1-2/+37
Add SDHI nodes to the DT of the r8a7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add I2C and IIC supportBiju Das1-2/+125
Add the I2C[0-5] and IIC[0,1,3] devices nodes to the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add [H]SCIF{A|B} supportBiju Das1-3/+254
Describe [H]SCIF{|A|B} ports in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SMP supportBiju Das1-6/+32
Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Also add cpu1 phandle node to the PMU interrupt-affinity property. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add Ethernet AVB supportBiju Das1-1/+7
Add Ethernet AVB support for R8A7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add GPIO supportBiju Das1-4/+98
Describe GPIO blocks in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SYS-DMAC supportBiju Das1-0/+66
Describe SYS-DMAC0/1 in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1NBiju Das2-0/+16
Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Initial SoC device treeBiju Das1-0/+369
Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOMBiju Das1-0/+31
Add support for iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7743: Remove legacy "renesas,rcar-thermal" compatibilityGeert Uytterhoeven1-2/+1
The thermal hardware description for the RZ/G1M SoC was added to its DTS after the introduction of support for thermal zones, and included a thermal-zones node from the beginning. Hence there is no need to claim compatibility with "renesas,rcar-thermal", which would be needed only for backwards compatibility with kernels predating thermal zone support. Fixes: 6c76b4f7d89e89f0 ("ARM: dts: r8a7743: Add thermal device to DT") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: suniv: Add device tree for Lichee Pi NanoMesih Kilinc2-0/+28
Lichee Pi Nano is a F1C100s board by Lichee Pi. Add initial device tree for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-04ARM: dts: suniv: add initial DTSI file for F1C100sMesih Kilinc1-0/+147
F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-04ARM: dts: pxa3xx: Add Raumfeld DTS filesDaniel Mack9-0/+1006
This patch adds a set of DTS files that support all PXA3xx based Raumfeld audio hardware devices. Common nodes are factored out into 'common' and 'tuneable-clock' include files to keep the top-level DTS files smaller. Signed-off-by: Daniel Mack <daniel@zonque.org> [Robert: Reordered Makefile in alphabetical order] Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2018-12-04Merge tag 'arm-soc/for-4.20/devicetree-fixes' of ↵Olof Johansson2-2/+2
https://github.com/Broadcom/stblinux into fixes This pull request contains Broadcom ARM-based SoCs Device Tree fixes, please pull the following for 4.20: - Stefan fixes the polariy of the Wi-Fi reset GPIOs signals which would break on Raspberry Pi 3B and 3B+ * tag 'arm-soc/for-4.20/devicetree-fixes' of https://github.com/Broadcom/stblinux: ARM: dts: bcm2837: Fix polarity of wifi reset GPIOs Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-04Merge tag 'qcom-dts-for-4.21' of ↵Olof Johansson6-478/+10
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm Device Tree Changes for v4.21 * Add entry for Qualcomm TSENS thermal drivers * Update msm8974 thermal entries * Fix msm8974 Hammerhead magnetometer gpios * Add SoC specific compatibles for SDHC nodes * Remove Arrow SD600 eval board * tag 'qcom-dts-for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: qcom: Remove Arrow SD600 eval board ARM: dts: qcom: Add SoC-specific string for sdhci-msm-v4 nodes ARM: dts: qcom: msm8974-hammerhead: correct gpios property on magnetometer ARM: dts: msm8974: thermal: Add "qcom,sensors" property ARM: dts: msm8974: thermal: split address space into two MAINTAINERS: Add entry for Qualcomm TSENS thermal drivers Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-03Merge tag 'arm-soc/for-4.21/devicetree' of ↵Olof Johansson27-73/+156
https://github.com/Broadcom/stblinux into next/dt This pull request contains Broadcom ARM-based SoCs Device Tree changes for 4.21, please pull the following: - Rafal relicenses a bunch of DTS files he wrote under the GPL 2.0+/MIT license and adds proper SPDX license tags in the process - Rene adds support for the Linksys EA6500 v2 Wi-Fi router based on BCM4708 plus two BCM4360 and BCM4331 radios - Phil documents and updates the vchiq mailbox compatible string in order to establish a correct agreement between the Raspberry Pi firmware and the ARM CPU's view of what an ARM CPU cache line size is, he also fixes the mailbox "reg" property to be correctly expressed in bytes - Stefan updates the Raspberry Pi Zero DTS files to use SPDX tags - Florian enables the SATA PHY and AHCI controller on the BCM63138 SoCs, he also does a bit of refactoring of aliases for the Northstar Plus DTS files * tag 'arm-soc/for-4.21/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: BCM5301X: Describe Northstar pins mux controller ARM: dts: BCM5301X: Add basic DT for Linksys EA6500 V2 ARM: dts: bcm2835-rpi-zero: Switch to SPDX identifier ARM: dts: bcm283x: Correct mailbox register sizes ARM: dts: bcm283x: Correct vchiq compatible string dt-bindings: soc: Document "brcm,bcm2836-vchiq" ARM: dts: NSP: Move aliases to bcm-nsp.dtsi ARM: dts: BCM53573: Relicense SoC file to the GPL 2.0+ / MIT ARM: dts: BCM63xx: Enable SATA AHCI and PHY for BCM963138DVT ARM: dts: BCM63xx: enable SATA PHY and AHCI controller ARM: dts: BCM53573: Relicense Tenda AC9 file to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Relicense BCM47094 file to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Relicense BCM47081/BCM4709 files to the GPL 2.0+ / MIT Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-03ARM: dts: realview: Fix some more duplicate regulator nodesRob Herring2-4/+4
There's a bug in dtc in checking for duplicate node names when there's another section (e.g. "/ { };"). In this case, skeleton.dtsi provides another section. Upon removal of skeleton.dtsi, the dtb fails to build due to a duplicate node 'fixedregulator@0'. As both nodes were pretty much the same 3.3V fixed regulator, it hasn't really mattered. Fix this by renaming the nodes to something unique. In the process, drop the unit-address which shouldn't be present wtihout reg property. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-03ARM: dts: bcm2837: Fix polarity of wifi reset GPIOsStefan Wahren2-2/+2
The commit b1b8f45b3130 ("ARM: dts: bcm2837: Add missing GPIOs of Expander") introduced a wifi power sequence. Unfortunately the polarity of the reset GPIOs were wrong and broke the wifi support on Raspberry Pi 3 B and later in 3 B+. This wasn't discovered before since the power sequence takes only effect in case the relevant MMC driver is compiled as a module. Fixes: b1b8f45b3130 ("ARM: dts: bcm2837: Add missing GPIOs of Expander") Cc: stable@vger.kernel.org Reported-by: Matthias Lueschner <lueschem@gmail.com> Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=911443 Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-12-03ARM: dts: exynos: Add opp-suspend to DMC and leftbus devfreq OPPs on Exynos4Lukasz Luba2-0/+4
Mark as opp-suspend required devfreq Operating Performance Points to fix resuming issues on Exynos 4 boards. The patch is based on earlier work by Tobias Jakobi. Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Suggested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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