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2023-06-21ARM: dts: Move .dts files to vendor sub-directoriesRob Herring1-1253/+0
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2022-06-15ARM: dts: sunxi: Drop resets from r_pio nodesSamuel Holland1-1/+0
None of the sunxi pin controllers have a module reset line. This is confirmed by documentation (A80) as well as experimentation (A33). Let's remove the inaccurate properties. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220531053623.43851-3-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-04ARM: dts: sunxi: Add missing LVDS resets and clocksMaxime Ripard1-2/+6
Some old SoCs, while supporting LVDS, don't list the LVDS clocks and reset lines. Let's add them when relevant. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-20ARM: dts: sun9i: Remove useless reset and clock namesMaxime Ripard1-2/+0
The MMC configuration clock controller in the A80 definition has a clock-names and reset-names property, even though the binding for that controller doesn't declare it. Remove it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-20ARM: dts: sun9i: Make sure the USB PHY resources are in the same orderMaxime Ripard1-16/+16
While this is functional, it's a best practice to always have the clocks and reset lines in order, in case we ever need to have compatibility code. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-05Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+11
Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
2019-11-01ARM: dts: sun9i: a80: Add Security System nodeCorentin Labbe1-0/+9
The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A80 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-10-21ARM: dts: sun9i: Add missing watchdog clocksMaxime Ripard1-0/+2
The watchdog has a clock, but it wasn't always listed. Add it to the devicetree where it's missing. Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-04ARM: dts: sunxi: Revert phy-names removal for ECHI and OHCIMaxime Ripard1-0/+5
This reverts commits 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI"), 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") and 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI"). It turns out that while the USB bindings were not mentionning it, the PHY client bindings were mandating that phy-names is set when phys is. Let's add it back. Fixes: 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI") Fixes: 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") Fixes: 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI") Reported-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20191002112651.100504-1-mripard@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-08-23ARM: dts: sunxi: Add mdio bus sub-node to GMACChen-Yu Tsai1-2/+6
The DWMAC binding never supported having the Ethernet PHY node as a direct child to the controller, nor did it support the "phy" property as a way to specify which Ethernet PHY to use. What seemed to work was simply the implementation ignoring the "phy" property and instead probing all addresses on the MDIO bus and using the first available one. The recent switch from "phy" to "phy-handle" breaks the assumptions of the implementation, and does not match what the binding requires. The binding requires that if an MDIO bus is described, it shall be a sub-node with the "snps,dwmac-mdio" compatible string. Add a device node for the MDIO bus, and move the Ethernet PHY node under it. Also fix up the #address-cells and #size-cells properties where needed. Fixes: de332de26d19 ("ARM: dts: sunxi: Switch from phy to phy-handle") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-24ARM: dts: sunxi: Prefer A31 bindings for IRClément Péron1-1/+1
Since A31, memory mapping of the IR driver has changed. Prefer the A31 bindings instead of A13. Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Sean Young <sean@mess.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCIMaxime Ripard1-5/+0
Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-26ARM: dts: sun9i: Remove deprecated pinctrl propertiesMaxime Ripard1-5/+4
We switched to the generic pinctrl binding some time ago, yet the GMAC pinctrl node apparently slipped through. Fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Remove pinctrl size-cells propertyMaxime Ripard1-1/+0
The children nodes of the pinctrl node hadn't have any reg property for quite some time, so we don't need the size-cells property. Remove it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Fix the TCON output clockMaxime Ripard1-0/+1
Even though we shouldn't really have any external user of the clock provided by the TCON, if clock-output-names is set, then #clock-cells must be there as well. Fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sunxi: Fix GIC compatibleMaxime Ripard1-1/+1
As can be shown by the YAML schema now, the combination of GIC compatibles we were using has never been an option. Switch to the gic-400 variant, which is the more correct option. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun9i: Add missing unit addressMaxime Ripard1-1/+1
The soc node in the A80 DTSI has a ranges property, but no matching unit address, which results in a DTC warning. Add the unit address to remove that warning. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25ARM: dts: sun9i: Fix Display Engine DTC warningsMaxime Ripard1-52/+12
Our display engine endpoints trigger some DTC warnings due to the fact that we're having a single endpoint that doesn't need any reg property, and since we don't have a reg property, we don't need the address-cells and size-cells properties anymore. Fix those Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: Add A80 GMAC RGMII pinmux settingChen-Yu Tsai1-0/+13
The GMAC (gigabit ethernet controller) supports RGMII to connect to the ethernet PHY, for gigabit network speeds. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: Add A80 GMAC gigabit ethernet controller nodeChen-Yu Tsai1-0/+21
The A80 has the same GMAC found on the A31 SoC. Add a device node, and an alias for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: Add GMAC clock nodeChen-Yu Tsai1-0/+31
The A80 has the same DWMAC hardware as on earlier Allwinner SoCs. The accompanying GMAC clock register has been moved into the "System Control" area. Add a clock node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-14ARM: dts: sun9i: Fix I2C bus warningsRob Herring1-1/+1
dtc has new checks for I2C buses. The sun9i-a80 dts file has a node named 'i2c' which causes a false positive warning. As the node is a RSB bus, correct the node name to be 'rsb' to fix the warnings. arch/arm/boot/dts/sun9i-a80-cubieboard4.dtb: Warning (i2c_bus_reg): /soc/i2c@8003400/codec@e89:reg: I2C address must be less than 10-bits, got "0xe89" arch/arm/boot/dts/sun9i-a80-cubieboard4.dtb: Warning (i2c_bus_reg): /soc/i2c@8003400/pmic@745:reg: I2C address must be less than 10-bits, got "0x745" arch/arm/boot/dts/sun9i-a80-optimus.dtb: Warning (i2c_bus_reg): /soc/i2c@8003400/codec@e89:reg: I2C address must be less than 10-bits, got "0xe89" arch/arm/boot/dts/sun9i-a80-optimus.dtb: Warning (i2c_bus_reg): /soc/i2c@8003400/pmic@745:reg: I2C address must be less than 10-bits, got "0x745" Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-03-20ARM: dts: sun9i: Add pinmux settings for LCD0 RGB888 output.Chen-Yu Tsai1-0/+11
The A80 supports RGB888 with H/V sync from LCD0. Add a pinmux setting for the needed pins. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-20ARM: dts: sun9i: Add device nodes for documented display pipelines for A80Chen-Yu Tsai1-0/+381
The Allwinner A80 SoC has 3 display pipelines, of which some parts are documented: - 3x display front ends (FE), documented - 2x display enhancement units (DEU), undocumented - 3x display back ends (BE), documented - 2x dynamic range controller (DRC), undocumented - 2x LCDC/TCONs, documented - 1x LCDC/TCON, undocumented, and probably not useable - 1x HDMI transmitter, undocumented but DesignWare compatible - 1x MERGE block, function unknown This patch adds device nodes for the first 2 documented pipelines: FE0 - DEU0 - - BE0 - DRC0 - TCON0 x FE1 - DEU1 - - BE1 - DRC1 - TCON1 Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-10ARM: dts: sun9i: Add enable-method for SMP support for the A80 SoCChen-Yu Tsai1-0/+8
Using the enable-method property for SMP support would allow future PSCI implementations to override any in-OS support. This is better than just matching against the machine compatible, and then having to determine whether other methods are available or not. This adds enable-method properties to all CPU nodes. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-02-16ARM: dts: sun9i: Add secure SRAM node used for SMP hotplugChen-Yu Tsai1-0/+19
The A80 stores some magic flags in a portion of the secure SRAM. The BROM jumps directly to the software entry point set by the SMP code if the flags are set. This is required for CPU0 hotplugging. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-02-16ARM: dts: sun9i: Add PRCM device node for the A80 dtsiChen-Yu Tsai1-0/+5
The PRCM is a collection of clock controls, reset controls, and various power switches/gates. Some of these can be independently listed and supported, while a number of CPU related ones are used in tandem with CPUCFG for SMP bringup and CPU hotplugging. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-02-16ARM: dts: sun9i: Add CPUCFG device node for A80 dtsiChen-Yu Tsai1-0/+5
CPUCFG is a collection of registers that are mapped to the SoC's signals from each individual processor core and associated peripherals, such as resets for processors, L1/L2 cache and other things. These registers are used for SMP bringup and CPU hotplugging. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-02-16ARM: dts: sun9i: Add CCI-400 device nodes for A80Chen-Yu Tsai1-0/+46
The A80 includes an ARM CCI-400 interconnect to support multi-cluster CPU caches. Also add the maximum clock frequency for the CPUs, as listed in the A80 Optimus Board FEX file. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-10-13ARM: dts: sun9i: Change node names to remove underscoresMaxime Ripard1-5/+5
Some node names in the A80 DTSI still have underscores in them. Remove them in favour of hyphens to remove DTC warnings. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-06ARM: dts: sun9i: Rename pinctrl nodes to avoid warningsMaxime Ripard1-6/+6
Our pinctrl node names were containing unit-adresses without a reg property, resulting in a warning. Change the names for our new convention. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-06ARM: dts: sun9i: Remove skeleton to avoid warningsMaxime Ripard1-7/+2
Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-06ARM: dts: sunxi: Remove leading zeros from unit-addressesMaxime Ripard1-43/+43
Most of our device trees have had leading zeros for padding as part of the nodes unit-addresses. Remove all these useless zeros that generate warnings Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-27ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai1-2/+0
All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm/boot/dts/sun?i*.* arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra empty line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-26Merge tag 'clk-for-linus' of ↵Linus Torvalds1-297/+107
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
2017-02-07Merge tag 'sunxi-dt-for-4.11' of ↵Arnd Bergmann1-0/+3
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt Pull "Allwinner DT changes for 4.11" from Maxime Ripard: The usual chunk of DT changes, most notably: - Support for the H2+ and the V3s - CPUFreq support for the A33 - SPDIF support for the A31 and H3 - New boards: Beelink X2, Lichee Pi One, Lichee Pi Zero, Orange Pi Zero * tag 'sunxi-dt-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (42 commits) ARM: dts: sun8i-h3: Add SPDIF to the Beelink X2 ARM: dts: sun8i-h3: Add the SPDIF block to the H3 ARM: dts: sun8i-h3: Add SPDIF TX pin to the H3 ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB ARM: sun8i: sina33: Enable display ARM: sun8i: a23/a33: Add the oscillators accuracy ARM: sun8i: a23/a33: Enable the real LOSC and use it ARM: dts: sunxi: add support for Lichee Pi Zero board ARM: dts: sunxi: add dtsi file for V3s SoC ARM: dts: sun6i: sina31s: Enable USB OTG controller in peripheral mode ARM: dts: sun8i: reference-design: use AXP223 DTSI ARM: dts: sun8i: parrot: use AXP223 DTSI ARM: dts: sun8i: sina33: use AXP223 DTSI ARM: dts: sun8i: a33-olinuxino: use AXP223 DTSI ARM: dts: add DTSI for AXP223 dt-bindings: power: axp20x-usb: add axp223 compatible ARM: dts: sun7i: Add wifi dt node on Banana Pro ARM: dts: sun6i: Add SPDIF to the Mele I7 devicetree: bindings: Add vendor prefix for Shenzhen Xunlong Software ARM: dts: sun8i-h3: orange-pi-pc: Enable audio codec ...
2017-02-07ARM: DTS: Fix register map for virt-capable GICMarc Zyngier1-1/+1
Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-01-30ARM: dts: sun9i: Switch to new clock bindingsChen-Yu Tsai1-297/+107
Now that we have a full clock driver for sun9i, switch to it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-10ARM: dts: sunxi: Explicitly enable pull-ups for MMC pinsChen-Yu Tsai1-0/+3
In the past, all the MMC pins had allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; which was actually a no-op. We were relying on U-boot to set the bias pull up for us. These properties were removed as part of the fix up to actually support no bias on the pins. During the transition some boards experienced regular MMC time-outs during normal operation, while others completely failed to initialize the SD card. Given that MMC starts in open-drain mode and the pull-ups are required, it's best to enable it for all the pin settings. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-12-26ARM: sunxi: Convert pinctrl nodes to generic bindingsMaxime Ripard1-25/+25
Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-26ARM: sunxi: Remove useless allwinner,pull propertyMaxime Ripard1-7/+0
The allwinner,pull property set to NO_PULL was really considered our default (and wasn't even changing the default value in the code). Remove these properties to make it obvious that we do not set anything in such a case. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-12-26ARM: sunxi: Remove useless allwinner,drive propertyMaxime Ripard1-4/+0
The allwinner,drive property set to 10mA was really considered as our default. Remove all those properties entirely to make that obvious. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-22ARM: sunxi: Add the missing clocks to the pinctrl nodesMaxime Ripard1-2/+4
The pin controllers also use the two oscillators for debouncing. Add them to the DTs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-11-22ARM: dts: sun9i: Add mmc1 pinmux settingChen-Yu Tsai1-0/+8
On the A80, mmc1 is available on pingroup G. Designs mostly use this to connect to an SDIO WiFi chip. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-27ARM: dts: sun9i: Add missing #interrupt-cells to R_PIO pinctrl device nodeChen-Yu Tsai1-2/+1
The R_PIO device node is missing #interrupt-cells, which causes interrupt parsing to fail to match it as a valid interrupt controller. Add #interrupt-cells to it. Also remove the unnecesary #address-cells and #size-cells. Fixes: 1ac56a6da9e1 ("ARM: dts: sun9i: Add A80 R_PIO pin controller device node") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-22ARM: dts: sun9i: Switch to the AC100 RTC clock outputs for osc32kChen-Yu Tsai1-6/+5
The 32.768 kHz clock inside the A80 SoC is fed from an external source, typically the AC100 RTC module. Make the osc32k placeholder a fixed-factor clock so board dts files can specify its source. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-25ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pinsChen-Yu Tsai1-1/+2
mmc2_8bit_pins is used with eMMC chips, which also have a reset pin. The MMC controller also has a reset output that is supported. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-25ARM: dts: sun9i: Use sun9i specific mmc compatibleChen-Yu Tsai1-4/+4
sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA trigger levels can be increased. Also, the mmc module clock parent has a higher clock rate, and the sample and output delay phases are different. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-03ARM: dts: sun9i: Add NMI controller device nodeChen-Yu Tsai1-0/+8
The Allwinner A80 SoC has an NMI controller. NMI is an external interrupt pin exclusely used with PMICs and other system critical peripherals (such as RTC) in Allwinner's reference designs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01ARM: dts: sun9i: Add Reduced Serial Bus controller device node to A80 dtsiChen-Yu Tsai1-0/+21
This patch adds a device node for the Reduced Serial Bus (RSB) controller and the defacto pinmux setting to the A80 dtsi. Since there is only one possible pinmux setting for RSB, just set it in the dtsi. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>