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2017-10-20arm: dts: fix unit-address leading 0sRob Herring1-26/+26
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-02-06ARM: dts: STiH407-pinctrl: Add Pinctrl group for HW flow-controlLee Jones1-2/+10
Each serial port which supports HW flow-control should have 2 Pinctrl groups. One for when HW flow-control is in progress, where the IP will take over controlling the lines and another group which enables the lines to be toggled using GPIO mechanisms. Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-10-21ARM: dts: STiH407: DT fix s/interrupts-names/interrupt-names/Geert Uytterhoeven1-1/+1
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Peter Griffin <peter.griffin@linaro.org>
2016-09-14ARM: DT: STiH407: Add spdif_out pinctrl configPeter Griffin1-0/+8
This patch adds the pinctrl config for the spidf out pins used by the sasg codec IP. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org>
2016-09-14ARM: DT: STiH407: Add i2s_in pinctrl configurationPeter Griffin1-0/+24
This patch adds the pinctrl config for the i2s_in pins used by the uniperif reader IP. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org>
2016-09-14ARM: DT: STiH407: Add i2s_out pinctrl configurationPeter Griffin1-0/+23
This patch adds the pinctrl config for the i2s_out pins used by the uniperif player IP. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org>
2016-09-06ARM: dts: STiH407: Declare PWM Capture data lines via PinctrlLee Jones1-0/+3
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-09-02ARM: dts: STiH407-pinctrl: Update gpio-cells to 2Patrice Chotard1-26/+26
This patch allows to use second parameter to the gpio specifier, which is used to specify whether the gpio is active high or low. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-02ARM: dts: STiH407-pinctrl: Add pinctrl_rgmii1_mdio_1 nodePatrice Chotard1-0/+7
On 96board, we can't reuse rgmii1-mdio as the pin pio1 3 ( mdint ) is dedicated for user led green 1. So create rgmii1_mdio_1 for 96board on which only mdio and mdc pins are useful. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
2016-09-02ARM: dts: STiH407-pinctrl: Add i2c2_alt2_1 nodePatrice Chotard1-0/+7
Add missing pin muxing for I2C2 alternate 2. This i2c2 pin muxing is dedicated for 96board high speed expansion connector. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> [Lee: Correct spacing between nodes] Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
2016-09-02ARM: dts: STiH407: Move pio20 node to fix kernel warningPatrice Chotard1-9/+9
cat /sys/kernel/debug/pinctrl/921f080.pin-controller-front1/pingroups leads to the kernel warning: [ 86.083560] st-pinctrl 921f080.pin-controller-front1: failed to get pin(-517) name [ 86.091192] ------------[ cut here ]------------ [ 86.095897] WARNING: CPU: 0 PID: 1579 at drivers/pinctrl/core.c:1414 pinctrl_groups_show+0x144/0x16c [ 86.105072] Modules linked in: [ 86.108127] CPU: 0 PID: 1579 Comm: cat Tainted: G W 4.6.0-00011-g9ba82e2-dirty #5 [ 86.116728] Hardware name: STiH415/416 SoC with Flattened Device Tree [ 86.123194] [<c010fa90>] (unwind_backtrace) from [<c010bea8>] (show_stack+0x10/0x14) [ 86.130943] [<c010bea8>] (show_stack) from [<c038c5b0>] (dump_stack+0x98/0xac) [ 86.138167] [<c038c5b0>] (dump_stack) from [<c0129b58>] (__warn+0xe8/0x100) [ 86.145121] [<c0129b58>] (__warn) from [<c0129c20>] (warn_slowpath_null+0x20/0x28) [ 86.152681] [<c0129c20>] (warn_slowpath_null) from [<c03bf810>] (pinctrl_groups_show+0x144/0x16c) [ 86.161550] [<c03bf810>] (pinctrl_groups_show) from [<c0218a5c>] (seq_read+0x1ec/0x4c0) [ 86.169553] [<c0218a5c>] (seq_read) from [<c01f66f0>] (__vfs_read+0x20/0xd0) [ 86.176592] [<c01f66f0>] (__vfs_read) from [<c01f7414>] (vfs_read+0x7c/0x104) [ 86.183716] [<c01f7414>] (vfs_read) from [<c01f81a0>] (SyS_read+0x44/0x9c) [ 86.190585] [<c01f81a0>] (SyS_read) from [<c0108400>] (ret_fast_syscall+0x0/0x3c) [ 86.198158] ---[ end trace 1aa2e3ae820eeb3e ]--- Move the pincontroller pio20 node above the tsin4 node, which referred to it, fix this warning. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
2015-10-15ARM: dts: Fix RGMII pinctrl timingsMaxime Coquelin1-2/+2
These new re-timing values provides a better stability on Ethernet link. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: STi: DT: STiH407: Rename incorrect interrupt related bindingLee Jones1-4/+4
interrupts-names => interrupt-names Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add RMII pinctrl supportPeter Griffin1-0/+27
This patch adds the RMII pinctrl support for the Synopsys MAC on STiH407 SoCs. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TXPeter Griffin1-0/+18
This patch adds the pinconfig for IRB TX and IRB UHF. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add SD pinctrl config for mmc0 controllerPeter Griffin1-0/+15
This patch adds the missing SD pinctrl config for mmc/sd controller 0. This is required to enable the B2144A daughter board that exposes this controller as a sd slot. Signed-off-by: Nebil BEN MEFTEH <nebil.ben-mefteh@st.com> Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add systrace pin configurationPeter Griffin1-0/+12
This patch adds the pin config for systrace for STiH407 family silicon. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add NAND flash controller pin configurationPeter Griffin1-0/+23
This patch adds NAND flash support controller pin configuration for STiH407 family silicon. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin configPeter Griffin1-0/+13
This patch adds the pin configuration for the NOR flash controller. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add serial3 pinctrl configurationPeter Griffin1-0/+9
Add missing serial 3 pinctrl config. This can be used on b2206 HVK, where it defaults to PIO31[3] & PIO31[4], alternate 1. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Carmelo Amoroso <carmelo.amoroso@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configsPeter Griffin1-4/+235
This patch adds the spi pinctrl configurations for all SPI controllers, and also the alternate muxings which can be used depending on board design. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: STi: DT: STiH407: Add i2c3 alternate pin configsPeter Griffin1-1/+13
i2c3 controller can use several sets of pins depending on board design. This patch adds the missing alternate pinconfigs. Signed-off-by: Seraphin Bonnaffe <seraphin.bonnaffe@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-09-30ARM: STi: DT: STiH407: Add a cec0 pin definitionPeter Griffin1-0/+8
This pin setup provides the correct configuration in order to interact with the CEC HW. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Nicolas Vanhaelewyn <nicolas.vanhaelewyn@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family mtsin0 pinctrl configurationPeter Griffin1-0/+19
mtsin0 channel can only be configured for parallel data transfer. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsout1 pinctrl configurationPeter Griffin1-0/+12
tsout1 channel can only be configured for serial data tranfer. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsout0 pinctrl configurationPeter Griffin1-0/+28
tsout0 channel can be configured for either serial or parallel data transfer. Both pin configurations are provided. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin5 pinctrl configurationPeter Griffin1-0/+21
tsin5 can only be configured for serial data transfer. However depending on board design, two alternate tsin5 pin configurations are available, both in pin-controller-front0. pinctrl_tsin5_serial_alt1 is brought out on B2120 reference design as TSD on NIMB slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin4 pinctrl configurationPeter Griffin1-0/+24
tsin4 can only be configured for serial data transfer. However depending on board design, two alternate pin configurations are available. One in pin-controller-front0 and the other in pin-controller-front1. pinctrl_tsin4_serial_alt3 is brought out on B2120 reference design as TSC on NIMA slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin3 pinctrl configurationPeter Griffin1-0/+12
tsin3 channel can only be configured for serial data transfer. On B2120 reference design tsin3 is brought out as TSB on the NIMB slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin2 pinctrl configurationPeter Griffin1-0/+28
tsin2 channel can be configured for either serial or parallel data transfer. This patch adds the pinctrl config for both possibilities. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin1 pinctrl configurationPeter Griffin1-0/+28
tsin1 channel can be configured for either serial or parallel data transfer. This patch adds the pinctrl config for both possibilities. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-07-22ARM: STi: DT: Add STiH407 family tsin0 pinctrl configurationPeter Griffin1-0/+28
tsin0 and be configured as either serial or parallel. This patch adds the pinctrl config for both possiblities. On B2120 reference design tsin0 is brought out as TSA on the NIMA slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-04-30ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35Karim BEN BELGACEM1-0/+2
This will avoid programming the retime registers when not implemented - PIO5 : no retime registers assigned to pins 6 and 7 - PIO35 : pin 7 is reserved so no retime register assigned to it Signed-off-by: Karim BEN BELGACEM <karim.ben-belgacem@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21ARM: dts: Add STiH407 SoC supportMaxime Coquelin1-0/+615
The STiH407 is advanced multi-HD AVC processor with 3D graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU. Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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