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2022-09-16ARM: dts: at91: Add `atmel,usart-mode` required property to serial nodesSergiu Moga1-0/+11
Add the missing required DT property `atmel,usart-mode` to the serial nodes of Atmel/Microchip DT files. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220913142205.162399-4-sergiu.moga@microchip.com
2022-08-02Merge tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-13/+11
Pull ARM DT updates from Arnd Bergmann: "As usual, the bulk of the changes for the SoC tree are devicetree file updates, and most of these changes are for 64-bit embedded machines. As before, there are a ton of style cleanups, and additional hardware support for existing machines. Looking only at the new SoC, the notable additions are: - A whole family of Broadcom broadband SoCs, both 32-bit and 64-bit: BCM63178, BCM63158, BCM4912, BCM6858, BCM6878, BCM6846, BCM63146, BCM6856, BCM6855, BCM6756, BCM63148, and BCM6813. Each SoC comes with a corresponding reference board. - The new NXP i.MX93 SoC, the follow-up to the popular i.MX6 and i.MX8 embedded SoCs, now using Cortex-A55 cores and the Ethos-U65 NPU. - Qualcomm Snapdragon 8cx Gen3 (SC8280XP), the current high end of Arm based Laptop SoCs, and its automotive cousin, the SA8540P. The SC8280XP is used in the Lenovo Thinkpad X13s laptop that also gets added here in addition to the reference boards. - Allwinner H616, a newer version of the H6 SoC, targeted at Set-top-box applications. It comes with dts files for the Orange Pi zero2 single-board computer and the X96 Mate set-top-box - Marvell Prestera 98DX2530 (AlleyCat5), a network switch chip in the Armada SoC family based on the Cortex-A55 core. New machines based on previously supported SoCs include: - Several new machines on NXP i.MX platforms: multiple Toradex Colibri boards using the "Iris" and "Ixora" carriers, DH electronics i.MX8M Plus DHCOM and PDK2, TQ-Systems TQMa8MPQL, and phytech phyBOARD-Polis-i.MX8MM. - Google Chameleon v3 FPGA board based on Intel Arria10 and Stratix 10 Software Virtual platform, both in the SoCFPGA platform. - Two new wireless devices based on Broadcom SoCs: The Asus GT-AX6000 Router and the Cisco Meraki MR26 access point - Improved Chromebook support for both the Mediatek and Qualcomm SoC families brought added machines: Acer Chromebook 514 (MT8192), Acer Chromebook Spin 513 (MT8195) and a couple of SC7180 based machines including the Lenovo IdeaPad Chromebook Duet 3. - Xiaomi Mi Mix2s, LG G7 and LG V35 are mobile phones based on Qualcomm SDM845, while Mi 5s Plus is based on MSM8996. - Finally, there are a few development board on other chips: PCB8309 (Microchip lan966x), Radxa Rock Pi S (Rockchips RK3308) DH DRC Compact (ST STM32MP1) and Inforce IFC6560 (Qualcomm SDM660)" * tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (829 commits) dt-bindings: soc: bcm: use absolute path to other schema dt-bindings: soc: bcm: drop quotes when not needed dt-bindings: soc: microchip: use absolute path to other schema dt-bindings: soc: microchip: drop quotes when not needed ARM: dts: lan966x: keep lan966 entries alphabetically sorted ARM: dts: lan966x: add support for pcb8309 dt-bindings: arm: at91: add lan966 pcb8309 board ARM: dts: lan966x: Enable network driver on pcb8291 ARM: dts: lan966x: Disable can0 on pcb8291 ARM: dts: lan966x: Add gpio-restart dt-bindings: arm: aspeed: add Aspeed Evaluation boards arm64: dts: qcom: Add support for Xiaomi Mi Mix2s dt-bindings: arm: qcom: Add Xiaomi Mi Mix2s bindings dt-bindings: arm: qcom: Document lg,judyln and lg,judyp devices dt-bindings: arm: qcom: add missing SM6350 board compatibles dt-bindings: arm: qcom: add missing SM6125 board compatibles dt-bindings: arm: qcom: add missing SDM845 board compatibles dt-bindings: arm: qcom: add missing SDM636 board compatibles dt-bindings: arm: qcom: add missing SDM630 board compatibles dt-bindings: arm: qcom: add missing QCS404 board compatibles ...
2022-07-08ARM: dts: at91: sama5d2: Fix typo in i2s1 nodeRyan Wanner1-1/+1
Fix typo in i2s1 causing errors in dt binding validation. Change assigned-parrents to assigned-clock-parents to match i2s0 node formatting. Fixes: 1ca81883c557 ("ARM: dts: at91: sama5d2: add nodes for I2S controllers") Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> [claudiu.beznea: use imperative addressing in commit description, remove blank line after fixes tag, fix typo in commit message] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220707215812.193008-1-Ryan.Wanner@microchip.com
2022-07-04ARM: dts: at91: use generic name for reset controllerClaudiu Beznea1-1/+1
Use generic name for reset controller of AT91 devices to comply with DT specifications. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220610092414.1816571-2-claudiu.beznea@microchip.com
2022-07-04ARM: dts: at91: sama5d2: fix compilation warningClaudiu Beznea1-2/+0
Fix the following compilation warning: arch/arm/boot/dts/sama5d2.dtsi:371.29-382.6: Warning (avoid_unnecessary_addr_size): /ahb/apb/ethernet@f8008000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property also defined at arch/arm/boot/dts/at91-sama5d2_icp.dts:353.8-363.3 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220615080633.1881196-2-claudiu.beznea@microchip.com
2022-07-04ARM: dts: at91: sama5d2: fix compilation warningClaudiu Beznea1-10/+10
Fix the following compilation warning: Warning (simple_bus_reg): /ahb/apb/resistive-touch: missing or empty reg/ranges property Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220615080633.1881196-1-claudiu.beznea@microchip.com
2022-02-24ARM: dts: at91: Use the generic "crypto" node name for the crypto IPsTudor Ambarus1-3/+3
The DT specification recommeds that: "The name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model. If appropriate, the name should be one of the following choices:" "crypto" being the recommendation for the crypto nodes. Follow the DT recommendation and use the generic "crypto" node name for the at91 crypto IPs. While at this, add labels to the crypto nodes where they missed, for easier reference purposes. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220208111225.234685-1-tudor.ambarus@microchip.com
2022-02-24ARM: dts: at91: remove status = "okay" from soc specific dtsiClaudiu Beznea1-3/+0
Remove status = "okay" from SoC specific dtsi as this is the default state. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220207111523.575474-1-claudiu.beznea@microchip.com
2022-02-24ARM: dts: at91: sama5d2: Fix PMERRLOC resource sizeTudor Ambarus1-1/+1
PMERRLOC resource size was set to 0x100, which resulted in HSMC_ERRLOCx register being truncated to offset x = 21, causing error correction to fail if more than 22 bit errors and if 24 or 32 bit error correction was supported. Fixes: d9c41bf30cf8 ("ARM: dts: at91: Declare EBI/NAND controllers") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: <stable@vger.kernel.org> # 4.13.x Acked-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220111132301.906712-1-tudor.ambarus@microchip.com
2021-12-13ARM: dts: at91: sama5d2: Name the qspi clockTudor Ambarus1-0/+2
Naming clocks is a good practice. The atmel-quadspi driver supports an unnamed clock for the peripheral clock in order to be backward compatible with old DTs, but it is recommended to name the clocks on new DTs. The driver's bindings file requires the clock-names property, so name the clock. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211209102542.254153-1-tudor.ambarus@microchip.com
2021-04-12ARM: dts: at91: sama5d2/trivial: fix letter case for etm hex addressNicolas Ferre1-2/+2
Fix the etm node hex address to lower case for matching regexp specification and removing the additional warning that looks like: arch/arm/boot/dts/at91-sama5d2_ptc_ek.dt.yaml: /: 'etm@73C000' does not match any of the regexes: '@(0|[1-9a-f][0-9a-f]*)$', '^[^@]+$', 'pinctrl-[0-9]+' Reported-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07ARM: dts: at91: sama5d2: add ETB and ETM unit nameNicolas Ferre1-2/+2
Add unit address to the ETB and ETM nodes. It also allow us to get rid of the warnings: ../arch/arm/boot/dts/sama5d2.dtsi:43.6-57.4: Warning (unit_address_vs_reg): /etb: node has a reg or ranges property, but no unit name ../arch/arm/boot/dts/sama5d2.dtsi:59.6-73.4: Warning (unit_address_vs_reg): /etm: node has a reg or ranges property, but no unit name when we compile with W=1. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210402170139.140595-1-nicolas.ferre@microchip.com
2020-12-03ARM: dts: at91: sama5d2: fix CAN message ram offset and sizeNicolas Ferre1-3/+3
CAN0 and CAN1 instances share the same message ram configured at 0x210000 on sama5d2 Linux systems. According to current configuration of CAN0, we need 0x1c00 bytes so that the CAN1 don't overlap its message ram: 64 x RX FIFO0 elements => 64 x 72 bytes 32 x TXE (TX Event FIFO) elements => 32 x 8 bytes 32 x TXB (TX Buffer) elements => 32 x 72 bytes So a total of 7168 bytes (0x1C00). Fix offset to match this needed size. Make the CAN0 message ram ioremap match exactly this size so that is easily understandable. Adapt CAN1 size accordingly. Fixes: bc6d5d7666b7 ("ARM: dts: at91: sama5d2: add m_can nodes") Reported-by: Dan Sneddon <dan.sneddon@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Cristian Birsan <cristian.birsan@microchip.com> Cc: stable@vger.kernel.org # v4.13+ Link: https://lore.kernel.org/r/20201203091949.9015-1-nicolas.ferre@microchip.com
2020-12-03ARM: dts: at91: sama5d2: map securam as deviceClaudiu Beznea1-0/+1
Due to strobe signal not being propagated from CPU to securam the securam needs to be mapped as device or strongly ordered memory to work properly. Otherwise, updating to one offset may affect the adjacent locations in securam. Fixes: d4ce5f44d4409 ("ARM: dts: at91: sama5d2: Add securam node") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/1606903025-14197-3-git-send-email-claudiu.beznea@microchip.com
2020-09-16ARM: dts: at91: sama5d2: add missing flexcom spi node propertiesAlexandre Belloni1-0/+10
SPI nodes require #address-cells and #size-cells add those properties in the flexcom spi nodes. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20200831171129.3886857-8-alexandre.belloni@bootlin.com
2020-09-16ARM: dts: at91: add unit-address to memory nodeAlexandre Belloni1-1/+1
The memory node requires a unit-address, add it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20200831171129.3886857-7-alexandre.belloni@bootlin.com
2020-09-03ARM: dts: at91: fix sram nodesAlexandre Belloni1-0/+7
The ranges, #address-cells and #size-cells properties are mandatory, add them to the sram nodes. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20200831171129.3886857-4-alexandre.belloni@bootlin.com
2020-07-23Merge tag 'timers-v5.9' of ↵Thomas Gleixner1-6/+6
https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clock event/surce driver changes from Daniel Lezcano: - Add sama5d2 support and rework the 32kHz clock handling (Alexandre Belloni) - Add the high resolution support for SMP/SMT on the Ingenic timer (Zhou Yanjie) - Add support for i.MX TPM driver with ARM64 (Anson Huang) - Fix typo by replacing KHz to kHz (Geert Uytterhoeven) - Add 32kHz support by setting the minimum ticks to 5 on Nomadik MTU (Linus Walleij) - Replace HTTP links with HTTPS ones for security reasons (Alexander A. Klimov) - Add support for the Ingenic X1000 OST (Zhou Yanjie)
2020-07-11ARM: dts: at91: sama5d2: add TCB GCLKAlexandre Belloni1-6/+6
The sama5d2 tcbs take an extra input clock, their gclk. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200710230813.1005150-4-alexandre.belloni@bootlin.com
2020-06-07Merge tag 'usb-5.8-rc1' of ↵Linus Torvalds1-120/+0
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY driver updates from Greg KH: "Here are the large set of USB and PHY driver updates for 5.8-rc1. Nothing huge, just lots of little things: - USB gadget fixes and additions all over the place - new PHY drivers - PHY driver fixes and updates - XHCI driver updates - musb driver updates - more USB-serial driver ids added - various USB quirks added - thunderbolt minor updates and fixes - typec updates and additions All of these have been in linux-next for a while with no reported issues" * tag 'usb-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (245 commits) usb: dwc3: meson-g12a: fix USB2 PHY initialization on G12A and A1 SoCs usb: dwc3: meson-g12a: fix error path when fetching the reset line fails Revert "dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings" Revert "dt-bindings: usb: qcom,dwc3: Add compatible for SC7180" Revert "dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver" USB: serial: ch341: fix lockup of devices with limited prescaler USB: serial: ch341: add basis for quirk detection CDC-ACM: heed quirk also in error handling USB: serial: option: add Telit LE910C1-EUX compositions usb: musb: Fix runtime PM imbalance on error usb: musb: jz4740: Prevent lockup when CONFIG_SMP is set usb: musb: mediatek: add reset FADDR to zero in reset interrupt handle usb: musb: use true for 'use_dma' usb: musb: start session in resume for host port usb: musb: return -ESHUTDOWN in urb when three-strikes error happened USB: serial: qcserial: add DW5816e QDL support thunderbolt: Add trivial .shutdown usb: dwc3: keystone: Turn on USB3 PHY before controller dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property dt-bindings: usb: convert keystone-usb.txt to YAML ...
2020-05-25ARM: dts: at91: Remove the USB EP child nodeGregory CLEMENT1-120/+0
The endpoint configuration used to be stored in the device tree, however the configuration depend on the "version" of the controller itself. Then the EP child node are useless and describe as deprecated in the documentation binding: remove all the nodes from the SoC device tree file. Remove also the #address-cells and #size-cells properties that are no longer needed. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
2020-05-15ARM: dts: at91: sama5d2: Add missing flexcom definitionsTudor Ambarus1-0/+79
Describe all the flexcom functions for all the flexcom nodes. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-13-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Remove i2s and tcb aliases from SoC dtsiTudor Ambarus1-4/+0
Device aliases are board-specific, if needed one should define them in board dts rather than in the SoC dtsi. If an alias from the SoC dtsi is addressed by a driver that does not use any of the of_alias*() methods, we can drop it. This is the case for the i2s aliases, drop them. tcb aliases point to nodes that are not enabled in any of the sama5d2 based platforms. atmel_tclib.c is scheduled to go away, any board using that alias is already broken, so get rid of the tcb aliases too. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-14-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and I2C flx0 functionsTudor Ambarus1-0/+18
Spare boards of duplicating the DMA bindings. Describe the flx0 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-12-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add DMA bindings for the flx1 I2C functionTudor Ambarus1-0/+9
Spare boards of duplicating the DMA bindings. Describe the flx1 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-11-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add DMA bindings for the flx3 SPI functionTudor Ambarus1-0/+9
Spare boards of duplicating the DMA bindings. Describe the flx3 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-10-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and UART flx4 functionsTudor Ambarus1-0/+18
Spare boards of duplicating the DMA bindings. Describe the flx4 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-9-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Specify the FIFO size for the Flexcom UARTTudor Ambarus1-0/+2
The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs. Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-8-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx0 definitions in the SoC dtsiTudor Ambarus1-0/+40
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. There is a single functional change in this patch. With the move of the flx0 uart5 definition in the SoC dtsi, the uart5 from at91-sama5d27_wlsom1_ek.dts inherits the following optional property: atmel,fifo-size = <32>; This particular change was tested by Codrin. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-7-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx1 definitions in the SoC dtsiTudor Ambarus1-0/+29
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-6-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx2 definitions in the SoC dtsiTudor Ambarus1-0/+18
The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-5-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx3 definitions in the SoC dtsiTudor Ambarus1-0/+29
The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-4-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx4 definitions in the SoC dtsiTudor Ambarus1-0/+40
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-3-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-03-10ARM: dts: at91: sama5d2: use correct rtc compatibleAlexandre Belloni1-1/+1
Use the sama5d2 specific compatible string for the RTC. Link: https://lore.kernel.org/r/20191229204421.337612-8-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: dts: at91: sama5d2: set the sdmmc gclk frequencyLudovic Desroches1-0/+4
Set the frequency of the generated clock used by sdmmc devices in order to not rely on the configuration done by previous components. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20191128074522.69706-3-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: at91: sama5d2: mark secumod as a GPIO controllerAndrei Stefanescu1-1/+4
The Security Module exposes the PIOBU pins which an be used as regular GPIOs. The PIOBU pins are special because they do not lose their voltage during suspend-to-mem. This patch marks the secumod as a GPIO controller. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@microchip.com> [razvan.stefanescu@microchip.com Updated title] Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-2-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: at91: sama5d2: disable pwm0 by defaultRazvan Stefanescu1-0/+1
It will be enabled as needed by each board. Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-1-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-10-03ARM: dts: at91: sama5d2: add an rtc label for derived boardsKamel Bouhara1-1/+1
Add an rtc label so we just need to alias it from derived boards. Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com> Link: https://lore.kernel.org/r/20191002145914.14874-1-kamel.bouhara@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-04-08ARM: dts: sama5d{2,4}: use SPDX-License-IdentifierAlexandre Belloni1-38/+1
External E-Mail The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-03-28ARM: dts: at91: sama5d2: add labels to soc dtsi for derivative boardsNicolas Ferre1-3/+3
This adds labels to commonly used device-tree nodes so that derivative boards can avoid ahb/apb hierarchy. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-01-30ARM: dts: Kill off skeleton{64}.dtsiRob Herring1-1/+3
Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-11-21ARM: dts: at91: sama5d2: switch to new clock bindingAlexandre Belloni1-610/+60
Switch sama5d2 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-11-21ARM: dts: at91: sama5d2: use the divided clock for SMCRomain Izard1-1/+1
The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two different clocks for the peripherals in the SoC. The Static Memory controller is connected to the divided master clock. Unfortunately, the device tree does not correctly show this and uses the master clock directly. This clock is then used by the code for the NAND controller to calculate the timings for the controller, and we end up with slow NAND Flash access. Fix the device tree, and the performance of Flash access is improved. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-09-19arm: dts: sama5d2: Update coresight bindings for hardware portsSuzuki K Poulose1-7/+10
Switch to the new coresight bindings for hardware ports Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-27ARM: dts: at91/trivial: remove old NAND bindings leftover in sama5d2Nicolas Ferre1-38/+0
As the new bindings are already in place in sama5d2.dtsi and that it's used in the only Mainline board for this product (at91-sama5d2_ptc_ek.dts), we can safely remove the old bindings. Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-27ARM: dts: at91: sama5d2: add nodes for I2S controllersCyrille Pitchen1-0/+38
This patch adds DT nodes for I2S0 and I2S1. It also adds an alias for each I2S node. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [codrin.ciubotariu@microchip.com: removed unnecessary clock phandles] Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-27ARM: dts: at91: sama5d2: add I2S clock muxing nodesCodrin Ciubotariu1-0/+18
This patch adds two clock muxes for the two I2S buses present on sama5d2 platforms. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-27ARM: dts: at91: sama5d2: Add resistive touch deviceEugen Hristev1-0/+10
Add generic resistive touch device which is connected to ADC block inside the SAMA5D2 SoC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-08-27ARM: dts: at91: sama5d2: add channel cells for ADC deviceEugen Hristev1-0/+2
Preparing the ADC device to connect channel consumer drivers Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2017-12-31ARM: dts: at91: sama5d2: TC blocks are also simple-mfd and syscon devicesAlexandre Belloni1-2/+6
Add simple-mfd and syscon to the TC blocks to allow to register one of the channels as clocksource properly at boot time and free up the remaining channels for other use. Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-09 23:44:23 +0300