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2022-09-09ARM: dts: r9a06g032-rzn1d400-db: Enable CAN1Biju Das1-0/+28
The CN10/CN11 on RZ/N1-EB board are headers to add jumpers to select which CAN interface to route to the real CAN connector J16. For a normal use case either we need to wire CAN1 or CAN2, but not both. This patch enables CAN1 and disables CAN2 by default assuming CN10/CN11 is wired for CAN1. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220902062752.56841-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-29ARM: dts: r9a06g032-rzn1d400-db: Add switch descriptionClément Léger1-0/+115
Add the description for the switch, GMAC2 and MII converter. With these definitions, the switch ports 0 and 1 (MII ports 5 and 4) are working on the RZ/N1D-DB board. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220624144001.95518-16-clement.leger@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17ARM: dts: r9a06g032-rzn1d400-db: Enable rtc0Clément Léger1-0/+4
The RZ/N1D-DB board does have a battery to power the RTC. Enable the RTC device on this board. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Link: https://lore.kernel.org/r/20220608090850.92735-1-clement.leger@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-24ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeoutJean-Jacques Hiblot1-0/+5
60s is a sensible default value. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Link: https://lore.kernel.org/r/20220221095032.95054-5-jjhiblot@traphandler.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-07-23ARM: dts: Renesas RZN1D-DB Board base fileMichel Pollet1-0/+28
This adds a base device tree file for the RZN1-DB board, with only the basic support allowing the system to boot to a prompt. Only one UART is used, with only a single CPU running. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>